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| 2011-05-17 | NAND Flash controller complies with ONFI 3.0 Arasan's NAND Flash Controllers comply with the ONFI 3.0 specification while supporting fast transfer modes up to 400MTS with differential signalling on clock and data, and double data-rate transfers (DDR). |
| 2010-06-21 | Serdes chipset improves driver safety National Semiconductor debuts the FPD-Link III family of automotive-grade Serdes chipsets that improve driver safety by delivering clock, data, and real-time I²C bidirectional control, continuously over a single differential pair. |
| 2010-02-02 | Clock drivers pack 2:1 mux, 1:6 fanout buffer Clock drivers pack 2:1 mux, 1:6 fanout buffer |
| 2009-02-12 | Intro to M-LVDS, clock and data distribution apps Intro to M-LVDS, clock and data distribution apps |
| 2008-11-10 | Clock generator simplifies timing architectures Clock generator simplifies timing architectures |
| 2007-12-01 | USB 2.0 board design and layout guidelines This document discusses schematic guidelines when designing a universal serial bus (USB) system. |
| 2005-06-20 | Odd number divide by counters with 50% outputs, synchronous clocks Here are some techniques for designing odd number counters with synchronous clocks and 50 per cent outputs. |
| 2008-04-23 | Maxim unveils dual-output clock generator Maxim unveils dual-output clock generator |
| 2006-11-20 | NSC develops high-speed LVDS SerDes chipset National Semiconductor Corp. has introduced a high-speed LVDS serializer/deserializer chipset that serializes 24 bits of data over a single differential pair (2 wires) at a data rate of 1.03 Gbps. |
| 2006-05-31 | ON Semi adds interface ICs to clock management portfolio ON Semi adds interface ICs to clock management portfolio |
| 2005-09-27 | LVDS and LVPECL repeater, translator with 45ps total jitter Featuring low total jitter of 45ps, the new 4Gbps low-voltage differential signaling (LVDS) and low-voltage pseudo emitter-coupled logic (LVPECL) repeater and translator from Texas Instruments Inc. (TI) help ensure signal and clock integrity in various communications applications, including high-speed network routing, wireless base stations and 622MHz central office clock distribution, and they can also serve as translators in an array of consumer applications. |
| 2003-03-17 | Buffers minimize jitter in clock distribution Buffers minimize jitter in clock distribution |
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