- Article
(7) -
Forum
(0) -
Blog
(0)
total search7 articles
sort by relevance
sort by date
| 2006-12-04 | Improve transient immunity in MCU-based embedded design (4) This article is part of a tutorial series on how to improve transient immunity in microcontroller-based embedded design. It focuses on PCB power supply and floorplanning. |
| 2007-07-11 | Using graph-based synthesis for FPGA timing closure The increased effects of routing on FPGA path timing requires EDA tools to understand physical properties of the target device and analyze designs during the placement process in order to achieve timing closure. |
| 2007-07-11 | Cadence RTL synthesis tool targets chip-level interconnect The new component of Cadence Logic Design Team Solution integrates the Encounter RTL Compiler synthesis tool with the First Encounter floorplanning tool so that synthesis can get timing estimates from physical floorplanning data. |
| 2005-09-23 | Synopsys unveils its latest floorplanning, analysis solution Synopsys unveils its latest floorplanning, analysis solution |
| 2005-11-01 | Die, package design get closer Targeting designs headed for flip-chip packages, Synopsys' floor-planning and analysis tool enables concurrent die and package design flows. |
| 2001-05-01 | Power distribution for deep-submicron SoC designs Power grid verification is becoming an imperative in deep-submicron design. |
| 2001-05-01 | The need for an EDA API There are a lot of skepticism with Cadence's IE (Integration Ensemble) tool-with capabilities that include floorplanning, RTL synthesis, placement, routing, extraction and analysis. The arguments for a single tool that encompasses all these features are compelling, but will the tools live up to engineer's expectations? |
--- total search 7 articles, total 1 pages, The 1 Page ---
1
Most Popular Articles
Search EE Times India
Max's Cool Beans
Strange modes of transport and other "stuff"
Someone just pointed me at a YouTube video that claims to show the world's first e-powered multicopter flight...
