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| 2011-01-28 | STARC qualifies design tool for AMS reference flow STARC qualifies design tool for AMS reference flow |
| 2010-12-09 | Performing source control, team-based design Know the options for source version control to determine the best tool flow and methodologies for team-based development. |
| 2010-10-18 | Embedded initiative unveils new design flow tool Embedded initiative unveils new design flow tool |
| 2010-09-16 | Software tool simplifies touch system design Software tool simplifies touch system design |
| 2010-02-12 | The partitioning challenge of ASIC design into multiple FPGAs Partitioning a large ASIC design into multiple FPGAs can be challenging. Doing some upfront planning and selecting the right tool flow can make achieve a thoroughly verified ASIC and first-silicon success. |
| 2009-09-22 | Execs tackle ASIC, FPGA design challenges The ASIC versus FPGA debate took an interesting turn, as executives from two design tool firms offered duelling keynote address on the virtues of and challenges facing FPGA-based and ASICs-based SoCs designs |
| 2009-06-23 | Upgraded EDA tool adds flow-routing option Upgraded EDA tool adds flow-routing option |
| 2009-04-28 | FPGA tool suite touts domain-specific design flow FPGA tool suite touts domain-specific design flow |
| 2009-03-31 | Magma CEO upbeat on analogue push Despite difficult times, Magma CEO Madhavan remains upbeat about new products and the company's inroads in analogue EDA. |
| 2009-03-04 | Design a digital IF modem Here's the tool flow for designing a digital intermediate frequency modem using the DSP Builder Advanced Blockset. |
| 2009-03-02 | C-level functional qualification tool debuts C-level functional qualification tool debuts |
| 2009-02-02 | Zuken offers free downloadable CADSTAR tool Zuken offers free downloadable CADSTAR tool |
| 2008-12-03 | Design flow aims Lyrtech multi-processor systems Design flow aims Lyrtech multi-processor systems |
| 2005-12-27 | Picking the right computational model As the examples of state machines, data flow and continuous time models show, a software development tool can mix and match computation models to generate the right embedded solution for any application and hardware target. |
| 2005-12-27 | Picking the right computational model As the examples of state machines, data flow and continuous time models show, a software development tool can mix and match computation models to generate the right embedded solution for any application and hardware target. |
| 2007-10-18 | Design flow implements DSP algorithm in next-gen design Design flow implements DSP algorithm in next-gen design |
| 2007-09-21 | Chip makers, EDA vendors set up DFM coalition The Silicon Integration Initiative (Si2) has announced that top chip makers and EDA tool vendors have established a coalition to add DFM parameters to existing design flow. |
| 2007-08-01 | Next-gen transistor restarts chip scaling With IC industry heading towards a transition to high-k materials and metal-gate structures, the chipmakers can expect higher initial product costs, performance hits and tool changes in the process flow. |
| 2007-07-24 | Sequence tool enhances Faraday low power design flow Sequence tool enhances Faraday low power design flow |
| 2007-05-08 | IC analysis tool refines chip architecture IC analysis tool refines chip architecture |
| 2007-03-05 | Integrated DFM solutions remain scarce EDA has done a great job of raising awareness of design-for-manufacturing (DFM) issues, but integrated DFM solutions remain scarce, according to Walter Ng, senior director of platform alliances at Chartered Semiconductor Manufacturing. |
| 2007-03-05 | Freescale reports reduction in EDA tool flow Freescale reports reduction in EDA tool flow |
| 2007-01-29 | STARC to use Mentor's analyser tool in DFM flow STARC to use Mentor's analyser tool in DFM flow |
| 2006-05-19 | Altera deploys Synopsys' Star-RCXT for 65nm designs Synopsys Inc. has announced that Altera has deployed Synopsys' Star-RCXT extraction tool and HSIM FastSpice simulator for its FPGA design flow targeting TSMC 65nm Nexsys process technology. |
| 2005-09-16 | When infrastructure is essence: Open-Silicon automates the flow When infrastructure is essence: Open-Silicon automates the flow |
| 2005-11-15 | Freescale, Cadence make 'single vendor flow' tool deal Freescale, Cadence make 'single vendor flow' tool deal |
| 2001-04-26 | An introduction to the PLL library This application note describes where the PLL library fits in a design flow, and discusses the phase-domain models of PLLs. |
| 2001-05-24 | Using formality for RTL-to-gate in LSI Logic's FlexStream design flow Using formality for RTL-to-gate in LSI Logic's FlexStream design flow |
| 2001-05-24 | Using formality in LSI Logic's FlexStream design flow Using formality in LSI Logic's FlexStream design flow |
| 2001-05-24 | Using PrimeTime in LSI Logic's FlexStream design flow Using PrimeTime in LSI Logic's FlexStream design flow |
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