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| 2010-03-30 | How to deal with formal verification issues How to deal with formal verification issues |
| 2006-07-27 | Formal verification tool provides fine control over thoroughness Formal verification tool provides fine control over thoroughness |
| 2005-10-27 | Survey finds verification tool use largely unchanged from 2004 Survey finds verification tool use largely unchanged from 2004 |
| 2001-04-15 | Hierarchical physical design for million-gate ASICs Raw design size in million-gated ASICs can cripple physical design and timing closure and the viable solution is physical hierarchy. |
| 2001-05-24 | Using formality for RTL-to-gate in LSI Logic's FlexStream design flow This application note describes procedures and recommendations for using the Formality formal equivalence checking tool for RTL-to-gate equivalence checking. |
| 2001-05-24 | Using formality in LSI Logic's FlexStream design flow This application describes procedures and recommendations for using the Formality formal equivalence checking tool for Gate to Gate equivalence checking. |
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