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| 2010-06-22 | LatticeECP2/M dual boot usage guide With support for simple, inexpensive SPI flash devices, the LatticeECP2 and LatticeECP2M FPGA families add the capability to load a backup bitstream configuration, referred to as the "golden" image. |
| 2010-06-17 | Virtex-6, Spartan-6 ref designs meet PCI-SIG standard Xilinx continues its momentum for PCIe support by achieving PCI-SIG compliance and interoperability testing for PCIe 1.1 single-lane configuration for its Spartan-6 and Virtex-6 FPGA connectivity targeted reference design. |
| 2009-06-05 | LatticeECP3 hardware checklist This application note steps through critical hardware implementation items relative to the LatticeECP3 device. |
| 2009-05-18 | Guide to using LatticeECP3 sysCONFIG Configuration is the process of loading or programming a design into volatile memory of an SRAM-based FPGA. |
| 2009-02-24 | Nios II compact configuration system for Cyclone III Nios II compact configuration system for Cyclone III |
| 2008-11-28 | Indirect programming of SPI serial flash PROMs Read about hardware setup, file generation flow, and software flow for programming M25Pxx SPI configuration PROM through FPGA. |
| 2008-11-25 | In-system programming using an embedded MCU Read about CPLD, FPGA and configuration PROM families that provide in-system programmability and pin locking. |
| 2008-11-21 | Using a microprocessor to configure FPGAs Read about FPGA configuration via MCP and a system-level model for implementing an interface to configuration pins. |
| 2008-08-14 | SRAM-based FPGAs save board space Actel Corp. has added new ProASIC3 and ProASIC3EL FPGAs to its military-qualified product offerings. |
| 2008-04-21 | New system designer eases FPGA-based designs New system designer eases FPGA-based designs |
| 2008-03-11 | 65nm FPGAs target handheld devices SiliconBlue has offered low-power 65nm FPGAs, which carry their own non-volatile memory on-chip for holding configuration data and are intended for use in mobile phones and other handheld devices. |
| 2007-09-18 | Altera unveils plug & play SI tech Altera has unveiled a Plug & Play SI tech that claims to redefine FPGA use in high-performance systems by enabling a single card configuration to be plugged into any designated system slot while under system power. |
| 2007-04-13 | Configuring Xilinx FPGAs with SPI serial flash This application note shows the configuration of Xilinx Virtex-5 and Spartan-3E FPGA families with Serial Peripheral Interface (SPI) serial flash device. It describes the required connections as well as the configuration flow for the SPI mode. |
| 2006-09-12 | BittWare updates DSP/FPGA toolkit BittWare updates DSP/FPGA toolkit |
| 2005-12-08 | Intellitech releases next-gen SystemBIST IC Intellitech has announced a SystemBIST IC for FPGA configuration and embedded PCB self test. |
| 2004-12-10 | Reading user data from configuration PROMs Reading user data from configuration PROMs |
| 2001-04-12 | Configuring Xilinx FPGAs using an XC9500 CPLD and parallel PROM This application note describes a simple, low-cost design to configure any Xilinx FPGA in a serial configuration mode using a Xilinx XC9500 CPLD and any parallel PROM. |
| 2001-04-12 | Configuring Spartan-II FPGAs from parallel EPROMs This application note describes a simple CPLD-based interface design to configure a Spartan-II device from a parallel EPROM using the Slave Parallel configuration mode. |
| 2001-04-12 | Virtex series configuration architecture user guide Virtex series configuration architecture user guide |
| 2001-04-12 | Data generation and configuration for Spartan series FPGAs Data generation and configuration for Spartan series FPGAs |
| 2001-07-03 | Using The Internet To Repair Hardware In The Field This paper describes how reconfigurable systems comprised of IEEE Std1532-compliant devices can be tested and repaired via the Internet (or any network). |
| 2002-06-28 | Configuration quick start guidelines Configuration quick start guidelines |
| 2004-12-02 | C code for interfacing AVR to AT17LVXXX FPGA configuration memories C code for interfacing AVR to AT17LVXXX FPGA configuration memories |
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