gate array What is a gate array IC? Search results

What is a gate array IC?

A prefabricated IC that is partially finished with rows of the transistors and resistors built in but unconnected. The chip is completed by adhering the top metal layers that provide the interconnecting pathways. These final masking stages are less costly than designing a full custom chip from scratch, which requires a new photomask for every transistor and interconnection layer.

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2011-02-07	Crossover SoCs enable new business models Xilinx CTO feels that heterogeneous multi-core SoCs with FPGA fabric are set to change the IC landscape. The only thing missing are the standards to enable it.
2011-01-06	Xilinx FPGA carries 1,000 cores University of Glasgow scientists claim to have created a 1,000-core computer processor based on a Xilinx field programmable gate array (FPGA).
2007-12-15	Lower the cost of intelligent power control with FPGAs Combining a programmable solution with an industry-standard processor core can save time, money, and real estate.
2006-04-04	Mercury rolls Serial RapidIO IP core for Xilinx FPGAs Mercury announced the availability of a Mercury Serial RapidIO IP core for Xilinx Virtex and Spartan FPGA families.
2006-02-09	Xilinx announces PlanAhead V8.1 Xilinx Inc. has announced version 8.1 of its PlanAhead software, a hierarchical design and analysis solution for Virtex-4 and Spartan-3 FPGAs.
2006-02-06	Epson develops "smallest" gate array Epson develops "smallest" gate array
2006-01-25	Altium tool integrates FPGA system, board design Altium Ltd has announced support for a range of discrete 32bit ARM technology-based processors in Altium Designer 6.0 design software.
2002-12-11	ORCA Series 4 I/O User's Guide This application note outlines a user guide for the I/O operation of the ORCA Series 4 of FPGAs.
2002-12-11	ORCA Series 3 FPGAs Programmable I/O Cell (PIC): Logic, Clocking, Routing, and External Device Interface This application note describes the features and advantages of the ORCA Series 3 FGPA programmable I/O cell (PIC)
2002-06-28	Virtex-II Pro 3.3V PCI reference design This application note describes the Virtex-II Pro 3.3V PCI solution.
2002-10-17	Using the ispPAC30 to Monitor Die Temperature in the ORCA-4 and FPSC ICs This application note describes how the ispPAC30 is suited to perform temperature monitoring in FPGAs and FPSCs.
2005-09-09	Xilinx, IP supplier partner on single-FPGA H.264 video encoder Claiming an industry first, programmable logic supplier Xilinx Inc. and intellectual property (IP) core supplier 4i2i Communications Wednesday (Sept. 7) launched a high-definition H.264 video encoder in a single field-programmable gate array (FPGA).
2005-08-23	LatticeXP FPGAs exhibit sharp drop in standby current Lattice Semiconductor has added a power-saving feature to its line of LatticeXP family of non-volatile field programmable gate arrays.
2002-06-28	Two flows for partial reconfiguration: Module based or small bit manipulations This application note describes the steps required to design, implement, verify and reconfigure the Virtex and Spartan series of FPGAs using module-based and small-bit method of partial reconfiguration.
2002-06-28	A quick JTAG ISP checklist This application note describes a short list of considerations needed for optimum performance of ISP designs. The considerations apply to Xilinx ISP device families.
2002-06-12	CL10K technology white paper This application note details the LIBERATOR CL10K link processed logic device families, how to use them with Altera FPGAs, and manufacturing processes that must be considered.
2002-06-28	Programming an FPGA via e-mail This application note describes the process to program or reprogram an FPGA via an intranet or Internet connection.
2005-11-02	Soft ARM7 processor optimized for ProASIC3 FPGAs Actel Corp. started to sample three devices— M7A3P250, M7A3PE600 and M7A3P100— with CoreMP7
2005-11-18	FPGA development tool upgraded with new simulation capability Version 5.1 of the DSP Builder development tool from Altera is designed to enable FPGA designers to simulate an imported HDL design within The MathWorks Simulink environment.
2001-03-27	Interfacing the QDR to the Xilinx Spartan-II FPGA This application note introduces the enhanced Quad Data Rate (QDR) SRAM architecture, and describes the interface between this high-speed SRAM and the Xilinx Spartan-II FPGA.
2001-04-12	High-speed FIFOs in Spartan-II FPGAs This application note describes how to build high-speed FIFOs using the Block SelectRAM+ memory in the Spartan-II FPGAs.
2001-04-12	Using SelectI/O interfaces in Spartan-II FPGAs This application note describes how to take full advantage of the flexibility of the Spartan-II FPGA family's SelectI/O features and the design considerations to improve and simplify system-level design.
2001-04-12	Configuring Xilinx FPGAs using an XC9500 CPLD and parallel PROM This application note describes a simple, low-cost design to configure any Xilinx FPGA in a serial configuration mode using a Xilinx XC9500 CPLD and any parallel PROM.
2001-04-12	Configuring Spartan-II FPGAs from parallel EPROMs This application note describes a simple CPLD-based interface design to configure a Spartan-II device from a parallel EPROM using the Slave Parallel configuration mode.
2001-04-12	Data generation and configuration for Spartan series FPGAs This application note discusses various methods to configure Xilinx's series of Spartan FPGAs.
2001-04-12	The role of distributed arithmetic in FPGA-based signal processing This application note derives the distributed arithmetic (DA) algorithm in embedding DSP functions in FPGA devices, and provides examples that illustrate its effectiveness in producing gate-efficient designs.
2001-04-23	On-chip pull-up/Pull-down resistors This application note describes the importance of the on-chip pull-up and pull-down resistors in American Microsystems' gate array and standard cell libraries.
2001-04-23	Pad pieces This application note discusses American Microsystems' "Pad Piece" methodology in gate array and standard cell libraries.
2001-06-01	Single-mask simplicity needed for SoC The move to multimillion-gate chips made it necessary to adopt design-reuse strategies for new SoC devices.
2002-04-08	Designing FPGA signal-processing datapaths for SDR This article provides an overview of how several signal processing functions can be implemented in a field programmable gate array.

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