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2012-03-09	MATLAB, Simulink get code generation update MathWorks announces Release 2012a (R2012a) of its MATLAB and Simulink product families newly incorporating HDL Coder and HDL Verifier.
2010-11-30	Adding MCU into FPGA design Know how to instantiate an MCU directly into the HDL and used it immediately in a standard FPGA design flow without special scripts or complicated steps.
2010-08-23	Upgraded tool suite enhances CPLD design Lattice Semiconductor Corp. unveils version 1.4 of its ispLEVER Classic design tool suite to include Synopsys Synplify Pro with the HDL Analyst feature set, and an ispMACH 4000ZE CPLD fitter.
2009-03-05	Unifying hardware, software verification Explore the need for a unified platform for both hardware and embedded software development.
2008-12-11	Aldec rolls out ALINT 2008.10 Aldec Inc. says ALINT reduces risk when developing complex multi-million gate ASICs.
2008-11-19	Aldec unveils Riviera-PRO 2008.10 The Riviera-PRO 2008.10 is an HDL mixed-language simulator for multi-million gate ASIC and FPGA designs.
2008-11-10	Using the embedded JTAG ACE player Here's a reference design consisting of HDL IP and ACE software utilities that give flexibility in creating ISP solutions.
2006-10-04	Use processor-driven tests for functional verification This article discusses processor driven test bench methods in detail and presents their strengths and weaknesses. It examines the inherent value of combining PDT with traditional HDL test benches.
2005-12-28	A practical approach to reusing HDL code in FPGA designs A practical approach to reusing HDL code in FPGA designs
2008-07-17	Speed up down-converter implementation with rapid prototyping Using the right EDA tools, performance can be simulated, analysed and design characteristics automatically converted to generic HDL code appropriate for synthesis and FPGA implementation.
2008-01-01	The basics of constructing FPGA A sound knowledge of the FPGA development process enables technical leads, supervisors, managers, or systems engineers interface with FPGA designers more efficiently.
2007-12-24	Aldec introduces multi-threaded VHDL compilation Aldec has announced the release of Active-HDL 7.3 that includes multi-threaded HDL compilation, new waveform viewer and expanded VHDL 2006 construct support.
2007-11-23	Mentor, MathWorks collaborate on optimised FPGA design flow Mentor Graphics and MathWorks have collaborated on HDL generated by MathWorks Simulink HDL Coder in Mentor?s Precision suite of advanced synthesis products to provide a rapid path from Simulink models to FPGA implementation.
2007-06-20	Actel unveils block-based FPGA design Actel Corp. is unveiling SmartDesign, a graphical design entry capability that lets users graphically create block diagrams from prefabricated blocks from Actel's DirectCore and SmartGen IP libraries, and supports custom blocks written in HDL code.
2007-02-21	SystemVerilog fails to deliver on design SystemVerilog is widely applied to verification, however, design use lags due to concerns about tool support.
2006-11-16	Design RFICs faster, accurately A middle-of-the-road approach to RFIC design balances top-down fast design processes with bottom-up silicon accuracy to produce a predictable schedule and first-pass silicon.
2006-05-17	Lattice validates Aldec"s simulators for its devices Aldec Inc. has announced that Lattice Semiconductor Corp. has validated Aldec's Riviera and Active-HDL simulators for use with Lattice devices.
2005-12-22	Wrestling with functional verification When chip complexity reaches 10 million or 100 million gates, the answer may lie in rethinking both verification and design.
2005-12-06	Forte, Summit collaborate on design, verification flow Forte Design Systems and Summit Design have collaborated to deliver an integrated solution that combines the strengths of the Vista SystemC IDE and Cynthesizer SystemC synthesis products.
2001-03-30	Understanding the Warp report file for Ultra37000-devices This application note provides a comprehensive description of the report file generated by the Warp HDL synthesis tool for the Ultra37000 CPLDs.
2005-10-11	HDL tool suite cuts cycle times, respins HDL tool suite cuts cycle times, respins
2005-11-18	FPGA development tool upgraded with new simulation capability Version 5.1 of the DSP Builder development tool from Altera is designed to enable FPGA designers to simulate an imported HDL design within The MathWorks Simulink environment.
2001-03-01	Complex designs demand greater attention to data management Complex designs generate huge amounts of data. A data-centric methodology addresses the data management challenge by employing a design-centric rather than a tool-centric methodology.
2001-03-01	One approach for debugging of modified designs Two engineers describe a methodology of comparing old designs to new designs in order to validate the new one.
2001-03-20	Getting started converting .ABL files to VHDL This application note is intended to assist Warp users in converting designs written in DATA I/O's ABEL 7 HDL to IEEE 1076 VHDL.
2001-03-20	Abel-HDL vs. IEEE-1076 VHDL Abel-HDL vs. IEEE-1076 VHDL
2001-03-22	An Introduction to active-HDL FSM An Introduction to active-HDL FSM
2001-03-26	Targeting Cypress PLDs from the Leonardo Spectrum Environment This application note discusses how designs created in Exemplar Logic's Leonardo Spectrum HDL synthesis tool can be targeted to Cypress Semiconductor's PLDs.
2001-03-28	An introduction to active-HDL Sim An introduction to active-HDL Sim
2001-05-01	Optimizing ASIC design flow for SoPCs System-on-programmable-chip technology has characteristics of both board-based design and ASIC-based SoC design. The immediate attraction of SoPC is that the design can be up and running very quickly.

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