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| 2012-05-17 | Utilise hierarchical methods for power intent specification Utilise hierarchical methods for power intent specification |
| 2011-01-24 | RTL-to-GDSII reference flow optimised for 32/28nm Magma Design Automation says its hierarchical RTL-to-GDSII reference flow is now available for the Common Platform alliance's 32/28nm low-power process technology. |
| 2010-07-27 | Runtime case study: Flat vs. hierarchical Runtime case study: Flat vs. hierarchical |
| 2008-04-25 | Energy conservation in portable devices (3) This article addresses the hierarchical approach to low power design of portable devices starting with process and transistor technology. |
| 2007-08-17 | Xilinx expands functionality of PinAhead tech Xilinx has announced the immediate availability of version 9.2 of its PlanAhead hierarchical design and analysis design tool. |
| 2006-09-06 | Xilinx releases analysis software to support 65nm FPGAs Xilinx Inc. has announced the availability of the 8.2 version of its PlanAhead hierarchical design and analysis software with support for the company's latest Virtex-5 LX family of 65nm FPGAs. |
| 2006-08-30 | PlanAhead ver.8.2 supports Xilinx Virtex-5 LX family Xilinx has upgraded its PlanAhead hierarchical design and analysis software to version 8.2 version with support for the Virtex-5 LX family of 65nm FPGAs. |
| 2006-02-09 | Xilinx announces PlanAhead V8.1 Xilinx Inc. has announced version 8.1 of its PlanAhead software, a hierarchical design and analysis solution for Virtex-4 and Spartan-3 FPGAs. |
| 2006-01-27 | Physical synthesis tool combines flat, hierarchical design Physical synthesis tool combines flat, hierarchical design |
| 2005-12-16 | Unified methodology enables full-chip test The article will discuss shortcomings of today's test flows and propose a unified methodology for implementing full-chip test. |
| 2005-10-07 | New design flow for ARM Cortex-A8 processor from Synopsys New design flow for ARM Cortex-A8 processor from Synopsys |
| 2001-03-22 | Using hierarchy in VHDL design Using hierarchy in VHDL design |
| 2001-04-15 | Hierarchical physical design for million-gate ASICs Hierarchical physical design for million-gate ASICs |
| 2001-05-01 | Cadence's 'all-in-one' tool gets skeptic reviews Cadence's Integration Ensemble (IE) is the first single tool that can take a hierarchical chip design all the way from synthesizable RTL code through a GDSII layout file and designers are raising an eyebrow if it will perform as well as it promises. |
| 2001-05-28 | Hierarchical hints Hierarchical hints |
| 2001-06-16 | Berkeley spin-off to spread use of Ptolemy tools Enhancements are on their way for Agile Design Inc.'s Ptolemy hierarchical simulation tools to boost engineering designs. |
| 2001-09-16 | Hopper hierarchical flow: Improvements for large ICs Hopper hierarchical flow: Improvements for large ICs |
| 2001-11-16 | Custom FPGA-based emulators accelerate IC design Custom FPGA-based emulators accelerate IC design |
| 2002-01-01 | Articulating hierarchical design for SoCs Articulating hierarchical design for SoCs |
| 2002-03-16 | ...Divide and conquer' with hierarchical design ...Divide and conquer' with hierarchical design |
| 2003-02-03 | Delivering a full-chip hierarchical circuit simulation Delivering a full-chip hierarchical circuit simulation |
| 2004-08-02 | Physical design flow taps partition layout Physical design flow taps partition layout |
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