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| 2011-05-12 | Cadence enhances Silicon Realisation with Altos buy Cadence buys Altos, an EDA vendor of SoC implementation tools while further enhancing its end-to-end Silicon Realisation portfolio. |
| 2011-04-01 | A unifying open-source EDA database remains a dream Unfortunately, a decade after its inception, the idea of a grand unifying open-source database providing interoperability without translation between all IC implementation tools has yet to be realised. |
| 2010-08-04 | Development tools key to SoC implementation Development tools key to SoC implementation |
| 2009-05-08 | FPGA framework simplifies app implementation FPGA framework simplifies app implementation |
| 2008-09-12 | Power considerations in designing with 90 nm FPGAs Reducing power in FPGA designs is a matter of making the right choices from the very beginning. |
| 2008-07-17 | Speed up down-converter implementation with rapid prototyping Speed up down-converter implementation with rapid prototyping |
| 2008-06-12 | Design tools target ARM core Design tools target ARM core |
| 2008-04-21 | New system designer eases FPGA-based designs Synplicity has introduced System Designer, a device-independent IP configuration and system-level assembly environment that has been added to Synplicity?s Synplify Pro and Synplify Premier FPGA design implementation tools. |
| 2007-08-07 | Overcoming Wireless USB commercialization challenges Simulation tools, isolation techniques and a test chip can all ease the burden of migrating to a single-chip solution. An architecture optimized for single-chip implementation further simplifies the process. |
| 2007-03-05 | Analysis tool cuts power consumption in nanometer ICs Magma Design Automation has introduced a pair of low-power IC implementation and analysis tools that have been shown to reduce power consumption in nanometer ICs by 25 per cent. |
| 2007-01-19 | Clear Shape, STARC partner in DFM flow Clear Shape Technologies Inc. announced a partnership with STARC to jointly develop, validate and deploy a variability-aware DFM flow. The flow includes InShapeT for systematic variability analysis that enables optimisation during implementation using commercial routing tools. |
| 2007-01-15 | Xilinx sets up R&D team in Singapore To assist in the development of its next-generation 45nm platform FPGA family, Xilinx Inc. has established an R&D team in its Asia-Pacific headquarters. This team will develop new design tools and implementation solutions to address the challenges of the 45nm process node. |
| 2006-07-31 | Tool suite promises more control over manufacturability Synopsis Inc. has said that PrimeYield predicts design-induced mechanisms that threaten manufacturing tolerances and provides automated correction guidance to upstream design implementation tools suite. |
| 2006-07-10 | EDA tool addresses sub-90nm process variations The requirement for EDA tools that addresses the design-for-variability problem at 90-, 65- and 45nm process nodes is driving faster adoption of the Pinnacle IC implementation EDA tool, said Sierra Design Automation. |
| 2006-04-05 | New video-compression standards work to meet test challenges Appropriate test and analysis tools can facilitate the development and implementation of new video-compression standards. |
| 2005-10-12 | Designing your embedded algorithms with high level graphical tools Designing your embedded algorithms with high level graphical tools |
| 2001-05-18 | Using boundary scan on the TMS320VC5420 This application note contains a description of the TMS320VC5420 DSP boundary scan implementation and information about how to use it with other boundary scan tools and devices. |
| 2001-05-22 | Using boundary scan on the TMS302VC5421 DSP This application note contains a description of the TMS302VC5421 DSP boundary scan implementation and information about how to use it with other boundary scan tools and devices. |
| 2001-05-23 | Using boundary scan on the TMS320VC5441 This application note contains a description of the TMS320VC5441 DSP boundary scan implementation and information about how to use it with other boundary scan tools and devices. |
| 2004-11-30 | Serial numbering implementation Serial numbering implementation |
| 2004-12-09 | PPC405 lockstep system on ML310 This app note discusses the implementation of a processor lockstep system using embedded PowerPC 405 (PPC405) processors in Xilinx Virtex-II Pro FPGAs, along with Xilinx software tools. |
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