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| 2010-10-18 | Embedded initiative unveils new design flow tool Embedded initiative unveils new design flow tool |
| 2009-06-23 | Start-up to demo asynchronous synthesis tool Start-up to demo asynchronous synthesis tool |
| 2007-07-11 | Cadence RTL synthesis tool targets chip-level interconnect Cadence RTL synthesis tool targets chip-level interconnect |
| 2007-03-28 | Tool automatically adds clock-gating logic to RTL code Tool automatically adds clock-gating logic to RTL code |
| 2007-03-02 | Mentor, MathStar to develop FPOA design tools Mentor, MathStar to develop FPOA design tools |
| 2006-11-07 | Xilinx unveils new design solution for Virtex-5 LXT Xilinx unveils new design solution for Virtex-5 LXT |
| 2006-05-11 | PLD tool gets upgrade, supports 90nm FPGAs PLD tool gets upgrade, supports 90nm FPGAs |
| 2006-02-17 | IC tool reduces design obstacles IC tool reduces design obstacles |
| 2006-02-03 | Engineer designs tool to generate logic specs Engineer designs tool to generate logic specs |
| 2006-01-16 | Xilinx adds embedded, DSP, RT debug design flows to tool Xilinx adds embedded, DSP, RT debug design flows to tool |
| 2005-10-27 | Altera releases enhanced Quartus II PLD design tool Altera releases enhanced Quartus II PLD design tool |
| 2005-11-10 | PLD tool suite gives more control to the designer PLD tool suite gives more control to the designer |
| 2000-12-05 | FACT I/O model kit This application note provides the SPICE information necessary to allow the customer to perform system level interconnect modeling for the Motorola FACT logic family. It is not intended for the purpose of performing extensive device modeling. |
| 2001-05-24 | Using formality for RTL-to-gate in LSI Logic's FlexStream design flow Using formality for RTL-to-gate in LSI Logic's FlexStream design flow |
| 2001-05-24 | Using formality in LSI Logic's FlexStream design flow Using formality in LSI Logic's FlexStream design flow |
| 2001-05-24 | Using PrimeTime in LSI Logic's FlexStream design flow Using PrimeTime in LSI Logic's FlexStream design flow |
| 2004-08-16 | Timing closure: Hybrid optimization to the rescue Hybrid optimization combines ASIC cell-based design flow with transistor-level optimization to achieve improvement in timing closure. |
| 2005-03-16 | Lower costs through design tool performance Lower costs through design tool performance |
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