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| 2010-12-08 | CPLD family cuts power usage by 50% Altera Corp. has started shipping its expanded MAX V CPLD family that promises to deliver low power and high performance for wireline, wireless, industrial, consumer, computer/storage, automotive, broadcast and military apps. |
| 2010-06-16 | Highest density FPGAs pack 820K logic elements Highest density FPGAs pack 820K logic elements |
| 2009-09-16 | 40nm FPGA tailored for high-end digital apps Altera Corp. has extended its high-end density range of its 40nm Stratix IV E FPGAs to 820K logic elements (LEs). |
| 2007-07-02 | Low-cost FPGAs support GbE, PCIe, RapidIO Altera Corp. has officially rolled out a line of entry-level FPGAs that handles 2.5Gbps data rates at a cost of $50 for a device providing 50,000 logic elements. |
| 2007-05-03 | Efficient 8X oversampling asynchronous serial data recovery using IDELAY This document describes IDELAY, the high-precision programmable delay elements associated with every input pin of Xilinx Virtex-4 and Virtex-5 devices. IDELAY can be used for the implementation of an oversampler that uses very few FPGA logic resources and just a single DCM and two global clock resources to do 8X oversampling. This solution provides better jitter tolerance than techniques that use multiple DCMs. |
| 2006-05-08 | Altera ships second member of Stratix ll GX FPGAs Altera Corp. has announced that it has begun shipping the second member of its Stratix II GX family, the EP2SGX90F, featuring 16 multi-gigabit transceivers and 90,000 logic elements. |
| 2001-05-24 | Using Multibit register inference to save area and power This application note describes a technique to use multi-bit register elements (even when they are excluded in the library) by creating netlist-based modules of flip-flops. |
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