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| 2009-11-25 | Why voltage-aware verification strategy counts Why voltage-aware verification strategy counts |
| 2009-05-15 | Complex SoCs power intent verification Complex SoCs power intent verification |
| 2009-04-13 | Platform delivers faster verification Platform delivers faster verification |
| 2009-03-24 | IEEE sanctions new low-power standard IEEE sanctions new low-power standard |
| 2008-12-15 | Constant analysis aids low-power design Constant analysis aids low-power design |
| 2008-06-05 | Synopsys define 'first' low-power verification methodology Synopsys define 'first' low-power verification methodology |
| 2007-01-29 | Architect, design, implement, and verify low-power digital ICs Architect, design, implement, and verify low-power digital ICs |
| 2007-08-27 | Verifying your low-power designs Verifying your low-power designs |
| 2007-06-20 | Synopsys acquires ArchPro Synopsys has acquired ArchPro Design Automation to extend its leadership in low power design and verification. |
| 2007-04-02 | Synopsys rolls design platform supporting UPF 1.0 Synopsys Inc. has announced a low-power design flow that will implement the Accellera Unified Power Format version 1.0 in its IC verification and implementation products in the second half of 2007. |
| 2007-03-15 | Cadence solution enables Taiwan's first 65nm IC design Cadence Design announced that Global Unichip was the first Taiwan-based design company to complete a successful tape-out of a 65nm device with the use of Cadence Low-Power Solution and SoC Encounter GXL RTL-to-GDSII system. |
| 2007-02-27 | EDA 'troublemakers' debate at DVCon EDA vendor The annual "EDA Bigwigs" panel at the Design and Verification Conference (DVCon) was renamed the "Troublemaker's Panel" this year for good reason. Confronted with provocative questions, DVCon EDA vendor representatives debated topics such as low-power standards, Cadence Design Systems' Skill language, and outsourcing to India. |
| 2007-02-02 | Cadence develops 'first' complete low-power solution Cadence develops 'first' complete low-power solution |
| 2007-01-25 | Virage Logic joins Si2's Low Power Coalition Virage Logic joins Si2's Low Power Coalition |
| 2006-11-07 | Cadence, Si2 partner for low-power design standard Cadence, Si2 partner for low-power design standard |
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