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| 2012-05-17 | Cadence working on "faster version" of Spice Cadence said it is working on a next-generation Spice that can simulate a 29-Gigabyte memory in "a matter of hours." |
| 2012-01-20 | How to employ critical area analysis Critical area analysis is a DFM technique that measures the susceptibility of a specific layout to random defects and indicates areas of the layout where design modifications can have the greatest positive impact on overall yield. |
| 2011-08-23 | How to configure an asymmetric multi-core app for DSPs Learn how to configure the memory resources of several example multi-core DSP applications properly so that they support asymmetric processing on Freescale StarCore DSPs. |
| 2011-08-19 | Understanding parameterizable content-addressable memory Understanding parameterizable content-addressable memory |
| 2011-05-09 | Use thicker copper to achieve high-current drive in power ICs Find out how thicker copper needed for higher currents and voltages can be implemented in power IC design. |
| 2011-04-15 | DDR4 IP solution with optimised integration debuts Cadence team debuts a DDR4 IP solution and integration environment that claims to speed integration, reduce cost and ensure design manufacturability. |
| 2011-02-18 | Bus master DMA performance demo ref design for Xilinx PCIe Bus master DMA performance demo ref design for Xilinx PCIe |
| 2011-02-16 | Interfacing QDR II SRAM devices with Virtex-6 FPGAs Here's a Verilog reference design that has been simulated, synthesized, and verified on hardware using Virtex-6 FPGAs and QDR II SRAM two-word burst devices. |
| 2010-11-23 | Bus Master DMA demo for PCIe Learn how to design and implement a Bus Master Direct Memory Access using PCI Express Endpoint solutions. |
| 2010-11-09 | SoC design IP reduces soft error rates SoC design IP reduces soft error rates |
| 2010-08-30 | Flowable chemical vapour deposition aids 20nm design Flowable chemical vapour deposition aids 20nm design |
| 2010-08-03 | Design and use considerations for NAND flash memory Design and use considerations for NAND flash memory |
| 2010-07-09 | How to build memory management for wired/wireless nets (Part 1 How to build memory management for wired/wireless nets (Part 1 |
| 2010-05-28 | Cadence, IBM team on high performance IPs Cadence Design Systems, Inc. and IBM have signed an agreement to develop DDR PHYs, memory controllers, and protocols such as PCIe and Ethernet under 32-nanometer silicon-on-insulator. |
| 2010-05-12 | iPad teardown reveals high processor-to-memory channel iPad teardown reveals high processor-to-memory channel |
| 2010-04-27 | Interfacing DDR memories with the i.MX31 This application note describes the different considerations and methods to route the double data rate (DDR) interface memory with the i.MX31. |
| 2010-04-22 | Energy management SoC packs flash memory Energy management SoC packs flash memory |
| 2010-03-03 | 96KB RAM MCU eases software design 96KB RAM MCU eases software design |
| 2010-02-26 | EC sets up task force for nanoscale memory project EC sets up task force for nanoscale memory project |
| 2010-02-15 | Hardware and layout design considerations for DDR3 SDRAM memory interfaces Hardware and layout design considerations for DDR3 SDRAM memory interfaces |
| 2009-08-11 | Elpida ventures into graphics memory Elpida ventures into graphics memory |
| 2009-06-30 | India Designs: Freescale's Kirin3 connectivity microcontrollers The MCF52xx (Kirin3) family of microcontrollers that delivers larger memory and more connectivity is an important milestone in Freescale India's design accomplishments. |
| 2009-05-20 | Digital potentiometer features on-chip EEPROM The integrated memory options in the CAT5140 save space and costs compared to DAC-based design approaches. |
| 2009-05-18 | Guide to using LatticeECP3 sysCONFIG Configuration is the process of loading or programming a design into volatile memory of an SRAM-based FPGA. |
| 2009-04-23 | IMEC sends DFM tool for embedded SRAMs to Samsung IMEC has successfully transferred the first EDA tool for statistical memory analysis to Samsung Electronics. |
| 2009-04-16 | Samsung dominates new iPod shuffle design Samsung dominates new iPod shuffle design |
| 2009-04-16 | Considerations in memory system design Considerations in memory system design |
| 2009-04-09 | JEDEC publishes new low power memory standard JEDEC publishes new low power memory standard |
| 2009-04-01 | SBC for 4G apps uses new Intel Xeon processor The Promentum ATCA-4500 combines high performance with large memory capacity and expansion flexibility. |
| 2009-02-25 | Design environment eases XDR memory development Design environment eases XDR memory development |
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