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| 2012-05-17 | Utilise hierarchical methods for power intent specification Here's a tutorial on using a hierarchical low-power design methodology. |
| 2012-01-25 | How formal MDV can take out IP integration uncertainty Find out how the formal metric-driven verification methodology and technologies can eliminate integration uncertainty through the automatic generation of Accellera-defined coverage metrics. |
| 2011-04-19 | Tuning VCP2 and TCP2 bit error rate performance Know the strategies and programming methodology to optimise VCP2 and TCP2 BER performance on TI DSPs. |
| 2011-03-07 | Synopsys, Xilinx unveil SoC design manual The practical guide to using FPGAs as a platform for SoC development includes design and verification expertise from several companies that have used FPGA-based prototyping to speed ASIC and SoC projects. |
| 2011-01-07 | Applications-driven design calls for new tools, methodologies Given an applications-driven design trend, productivity, predictability and profitability will become more imperative for success, says Cadence's Jaswinder Ahuja batting for new tools and methodologies. |
| 2010-12-20 | Solving the disappearing PCell mystery Read about a long-time programming methodology called "caching", which is used to proctect PCells. |
| 2010-12-03 | Design methodology transitions Design methodology transitions |
| 2010-11-29 | App modeling, mapping for system-level analysis Read about application modeling and mapping methodology that could be used for investigating the feasibility of new electronic products. |
| 2010-08-04 | EU project streamlines embedded system design The EU's SPEEDS (SPEculative and Exploratory Design in Systems Engineering) project has resulted in the definition of a design methodology, process and tool environment for model-based safety-critical embedded systems. |
| 2010-07-20 | Implementing Virtual Line Crossing Detection This article describes the implementation of Virtual Line Crossing Detection (VLCD) on an Altera Stratix II FPGA and the methodology we used. |
| 2010-06-29 | MindTree adopts Mentor's verification platform MindTree has joined Mentor Graphics' Questa Vanguard Programme and adopted a verification flow based on Mentor's Questa functional verification platform and the Open Verification Methodology. |
| 2010-06-21 | A numerical solution to an analogue problem This application note develops a methodology to approximate a function with an RC network. This methodology can be easily expanded to match any function and generate a discrete solution. |
| 2010-04-13 | High level synthesis enables low-power design The chip designer's most important task is to implement highly complex algorithms into hardware as quickly as possible, while still retaining power efficiency. High Level Synthesis (HLS) methodology has already been widely adopted as the best way to meet the challenge. |
| 2010-03-31 | Choosing system design methodologies: Part 2 This article looks at the requirements analysis, which captures informal descriptions of what a system, and techniques for more formally specifying system functionality, and how to turn such specifications into an architecture design. |
| 2009-12-29 | Timing closure methodology for advanced FPGA designs Timing closure methodology for advanced FPGA designs |
| 2009-12-21 | PCB power delivery network design methodology PCB power delivery network design methodology |
| 2009-12-15 | K-micro, Anritsu work to analyse 10G EPON chips K-micro (Kawasaki Microelectronics America) Anritsu have partnered to develop first test tool and methodology to analyse 10Gbps Ethernet Passive Optical Network (EPON) chips. |
| 2009-12-08 | CompZL user's guide This application note discusses the methodology for obtaining the required PID settings using automatic optimisation mode and manual mode, and offers an example scenario for comparison. |
| 2009-10-29 | Mechatronic apps welcome FPGAs Selecting the right electronic components and choosing the optimal design methodology is vital in developing a successful product. The flexibility of new components, such as FPGA devices, is intriguing. |
| 2009-07-09 | Pick the right MOSFET for flyback converter Read about a rigorous methodology for selecting the most appropriate MOSFET. |
| 2009-06-16 | Design guide for TinySwitch flyback Here's a design methodology for flyback power supply design using TinySwitch integrated off-line switchers. |
| 2009-05-14 | Topswitch-GX flyback design Here's a methodology for the design of Topswitch-GX family based off-line power supplies. |
| 2009-03-23 | Virtual vehicle: Wiring harnesses Here's a methodology that contains the necessary steps to ensure the creation of robust wiring harnesses. |
| 2009-03-05 | Error detection, recovery using CRC in FPGAs Know the ways of using the error detection CRC feature and test methodology to test the capability of this FPGA function. |
| 2009-02-24 | Verification beyond base classes Know the details of VMM applications, which are built on top of the VMM base classes. |
| 2009-02-19 | EDA software for 3-D stacked ICs unveiled 3D PathFinding extends the Javelin PathFinding methodology and j360 Silicon PathFinder platform. |
| 2009-02-12 | Initialise, program SGTL5000 Familiarise yourself with the code and methodology required to initialise and program the SGTL5000 using C code. |
| 2009-01-22 | Mentor announces TLM 2.0 design flow This scalable design methodology based on TLM allows a single model to be taken from design concept to implementation. |
| 2008-12-09 | Open source OVM solution rolls The Cadence solution lets users run both OVM and VMM VIP within a single OVM environment |
| 2008-11-28 | Cadence exec downplays Connections issue Pankaj Mayor said membership in Connections is fluid and that member companies changes constantly. |
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