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| 2001-03-30 | Understanding the Warp report file for Ultra37000-devices This application note provides a comprehensive description of the report file generated by the Warp HDL synthesis tool for the Ultra37000 CPLDs. |
| 2001-03-20 | Method to instantiate and use a core in Warp with Cypress CPLDs This application note describes in detail how customers can incorporate cores in their system-level designs. It contains a detailed description of the steps required to instantiate VIF files in both VHDL and Verilog designs. |
| 2001-03-20 | Method to instantiate and use a core in Synplify This application note is intended to assist people who use cores for Cypress Semiconductor's CPLDs and compile their design in Synplify. |
| 2001-03-20 | Method to instantiate and use a core in LeonardoSpectrum This application note is intended to assist people who use cores for Cypress Semiconductor's CPLDs and compile their design in LeonardoSpectrum. |
| 2001-03-21 | Method to instantiate and use a core in Warp Enterprise/Professional This application note contains a detailed description of the steps required to instantiate the core contained in the VIF file using the Warp Enterprise/Professional tool. |
| 2001-03-26 | Targeting Cypress PLDs from the Leonardo Spectrum Environment This application note discusses how designs created in Exemplar Logic's Leonardo Spectrum HDL synthesis tool can be targeted to Cypress Semiconductor's PLDs. |
| 2001-06-15 | Powerful low-cost synthesis for Actel ProASIC 500K family Powerful low-cost synthesis for Actel ProASIC 500K family |
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