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2012-03-09	Cadence digital flow accelerates 20nm design Cadence's latest RTL-to-GDSII design, implementation and signoff flow enables efficient power-performance-area trade-offs that support complex designs at advanced process nodes.
2012-03-05	Samsung's 20 nm DFM based on Mentor's Calibre platform The DFM sign-off solution is available for consumer and telecommunications designs targeting advanced process nodes.
2012-02-15	CEA-Leti showcases 22nm maskless lithography CEA-Leti demos a maskless lithography technology that meets the industry requirement for 14nm and 10nm process nodes.
2012-01-23	Towards the realm of app-specific solutions Altera feels the demands of new technology nodes are beginning to reach beyond the level of circuit design, requiring collaborative approach to find improvements in performance and energy efficiency.
2011-11-03	ARM acquires design optimisation firm, Prolific ARM Holdings has acquired an IC design optimisation software tool company, Prolific Inc. to help with process nodes at 20nm and below.
2011-06-14	Energy harvesting for wireless sensor nodes Energy harvesting for wireless sensor nodes
2011-05-05	Power leakage is a top concern Leakage power has become a top concern for IC designers in deep sub-micron process technology nodes (65nm and below) because it has increased to 30-50 per cent of total IC power consumption.
2010-05-12	IMEC, TSMC join forces on hybrid processes IMEC and TSMC have joined forces where IMEC will create application-driven variants of CMOS at more mature nodes and TSMC will further drive the process.
2009-11-23	Dealing with problems during timing closure As the process technology nodes keep shrinking, the variation of the design parameters transition becomes non-linear across different process, voltage and temperature (PVT) corners. Thus, we face problems during timing closure.
2009-06-01	Talus 1.1 delivers fast timing closure Magma has released Talus 1.1 that it says delivers the fastest timing closure on the most complex IC designs.
2009-05-08	Physical verification tools offer free trial Magma Design Automation has introduced the Quartz DRC and Quartz LVS 2009.05 physical verification tools.
2009-03-18	Design system accelerates chip development Lynx is optimised for Synopsys' Galaxy Design Platform and is configurable to incorporate third-party technology.
2008-12-16	Cadence unveils next-gen circuit simulator Cadence has unveiled the Virtuoso APS, the company's next-generation circuit simulator.
2008-11-17	An insider perspective of the semi industry Here's how chips are made, why ASICs cost so much, and what drives the industry to smaller process nodes.
2008-08-01	Digital video surveillance adds intelligence to networks Digital video formats in surveillance systems open up the possibility for local intelligence at the camera node to process the digital image stream, moving the system intelligence to the edge nodes rather than flooding the central monitor with low interest images.
2008-03-07	Mentor launches Calibre tools with Cell B.E. tech Mentor has released computational lithography tools accelerated with Cell/B.E. processor tech that have been qualified for production at IBM for 45nm and smaller process nodes.
2007-12-06	High-k dielectric process for CMOS eliminates gate leakage High-k dielectric process for CMOS eliminates gate leakage
2007-11-01	Dealing with IP at smaller process nodes Dealing with IP at smaller process nodes
2007-10-11	Cadence opens third R&D centre in Noida Cadence has announced the opening of a third R&D facility in Noida that will address the needs of engineers designing at 65 and 45-nm technology process nodes.
2007-09-17	S3 unveils 65nm mixed-signal IP chip for WiMAX S3 is taping out solutions, integrating IP into single-chip systems and producing more than 35 SoC designs at the 90nm and 65nm process technology nodes.
2007-07-23	Manufacturability-optimised reconfigurable logic for 65nm, 45nm nodes debuts Manufacturability-optimised reconfigurable logic for 65nm, 45nm nodes debuts
2007-05-28	Hynix joins IMEC's 32nm efforts Hynix has collaborated with European research centre IMEC to tackle memory challenges at the 32nm and below process nodes.
2007-05-03	Improve the industrial climate with better MCUs This article discusses examples of critical applications, where adding intelligence and processing horsepower closer to the nodes within the process can impact efficiency and reliability improvements. New SoC designs provide the intelligence necessary to make critical process measurements and enhance the control of these parameters.
2006-07-25	ArchPro targets power challenges with variable voltage tools In an interview with EE Times India, Pratap Reddy, chairman and CEO, ArchPro Design Automation Inc., discussed the nature of the power problems that ArchPro addresses. He described the EDA industry's response to challenges relating to power management that face IC designers, especially in advanced process nodes.
2006-07-10	EDA tool addresses sub-90nm process variations EDA tool addresses sub-90nm process variations
2005-09-01	Road map rethinks process reductions Road map rethinks process reductions

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