What is RTL?
| RTL stands for Register Transfer Level. It is a high-level hardware description language (HDL) used for defining digital circuits. The most popular RTL languages are VHDL and Verilog. |
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| 2012-05-23 | Uniquify becomes TSMC DCA partner In order to support TSMC's customers, Uniquify provides SoC integration, interface IP and manufacturing service. |
| 2012-05-21 | Cadence in-circuit acceleration aids system dev't Cadence's in-circuit acceleration offers a single heterogeneous environment for system-level verification, resulting in up-to-10x increased efficiency in system development. |
| 2012-05-16 | Cadence flow lowers n/w flow processor power Cadence Encounter RTL-to-GDSII flow enables a boost in performance as well as reduction in power consumption on the Netronome's low-power 'green' SoCs. |
| 2012-04-18 | Achieving early and accurate power analysis RTL power analysis offers the right trade-offs between accuracy and the ability to design for lower power. |
| 2012-03-09 | Cadence digital flow accelerates 20nm design Cadence's latest RTL-to-GDSII design, implementation and signoff flow enables efficient power-performance-area trade-offs that support complex designs at advanced process nodes. |
| 2011-11-15 | RTL tech optimised for power-sensitive apps RTL tech optimised for power-sensitive apps |
| 2011-10-26 | Avoiding RTL coding mistakes Avoiding RTL coding mistakes |
| 2011-09-16 | DSP design flow aims for medical imaging Altera presents model-based floating-point DSP design flow that integrates the algorithm modelling and simulation, RTL generation, synthesis, place and route, and design verification stages. |
| 2011-06-03 | Atrenta releases RTL design textbook Atrenta releases RTL design textbook |
| 2011-05-05 | NVIDIA licenses NextOp's BugScope Graphics company NVIDIA signs a multi-licence agreement with NextOp Software Inc. for expanded use of NextOp's BugScope assertion synthesis product. |
| 2011-04-15 | Facilitating at-speed test at RTL (Part 2 Facilitating at-speed test at RTL (Part 2 |
| 2011-04-11 | Facilitating at-speed test at RTL (Part 1 Facilitating at-speed test at RTL (Part 1 |
| 2011-01-24 | RTL-to-GDSII reference flow optimised for 32/28nm RTL-to-GDSII reference flow optimised for 32/28nm |
| 2010-12-07 | Melfas taps Magma's Talus for touch sensor chips Melfas taps Magma's Talus RTL, Vortex, and Power Pro tools and FineSim SPICE circuit simulation tool to implement two MCS-8000 touch sensor chips. |
| 2010-10-28 | Atrenta, TSMC join forces on synthesisable IP Atrenta Inc. and Taiwan Semiconductor Manufacturing Co. Ltd are cooperating to improve the quality of delivered synthesisable IP using Atrenta's SpyGlass platform. |
| 2010-10-08 | GN ReSound chooses Magma Design's Talus system Hearing instrument maker selects Talus RTL design solution for high-performance next-gen ICs for optimal power/performance trade-off. |
| 2010-06-04 | Tools bridge chip design, verification with shared database Jasper's upgraded ActiveDesign and JasperGold tools bridge chip design and verification by sharing a common, persistent knowledge base. |
| 2010-05-11 | Tool enables full-chip assertion synthesis EDA start-up NextOp rolls out initial product, dubbed BugScope, a full-chip assertion synthesis product that automatically generate functional coverage properties from testbench and RTL. |
| 2010-03-01 | Approaching RTL implementation with chip synthesis Approaching RTL implementation with chip synthesis |
| 2009-09-02 | RTL power tool packs sequential analysis RTL power tool packs sequential analysis |
| 2009-06-19 | Hardware design needs hardware design languages Read about the experiences in RTL market that are applicable to ESL. |
| 2009-06-01 | Talus 1.1 delivers fast timing closure Magma has released Talus 1.1 that it says delivers the fastest timing closure on the most complex IC designs. |
| 2009-05-15 | Complex SoCs power intent verification Know the basic elements of low power verification and how a technology enables power-aware verification at the RTL level. |
| 2009-04-29 | Talus IC implementation system supports CPF Talus becomes the first RTL-to-GDSII flow to support both the CPF and the Unified Power Format. |
| 2009-04-27 | FPGA start-up Achronix defying gravity FPGA start-up Achronix has the technology and financial stability to weather the current downturn, according to its CEO. |
| 2009-04-16 | Full-chip synthesis tool for advanced ICs upgraded Magma Design Automation Inc. has unveiled an upgraded version of Talus Design. |
| 2009-03-18 | Design system accelerates chip development Lynx is optimised for Synopsys' Galaxy Design Platform and is configurable to incorporate third-party technology. |
| 2009-03-18 | IP devt, FPGA prototyping with SystemC/TLM Here's a design flow that starts with highly abstracted models to cycle RTL models of IP. |
| 2009-03-02 | Jasper launches new verification tools Jasper Design Automation said it is automating IC design verification routines with a new suite of tools. |
| 2009-03-02 | C-level functional qualification tool debuts Certess' functional qualification software product targets companies developing SoCs or integrating IP blocks using C. |
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