Global Sources
EE Times-India
News
Products
Tech Articles
App Notes
 Forum  Blogs  White Papers  Webinars  eeUniversity
EE Times-India > Advanced Search > sequential logic

sequential logic Search results

 
 
total search4 articles sort by relevance sort by date
2009-02-09 Boost functional verification with SLEC
SLEC has the capability to formally verify RTL implementations against a specification in C/C++ or System C.
2006-02-03 Engineer designs tool to generate logic specs
Engineer designs tool to generate logic specs
2005-09-21 New frame buffer from Logic Devices
New frame buffer from Logic Devices
2001-03-28 State machine design considerations and methodologies
This application note describes the various options encountered during the state machine design cycle.
Most Popular Articles
  • Nokia brings on two Windows phones
  • Sony takes over handset biz from Ericsson JV
  • ARM-based tablets continue to reign
  • Intel's struggles outside the PC domain
  • ARM scales to 64bit architecture
  • Imec, partners aim for organic PV tech
  • e-cars look to gain perfect sound experience
  • Researchers study graphene photodetectors
  • Wearable energy storage devices power garments
  • Smartphone app packed car infotainment booms
    • Search EE Times India
    Max's Cool Beans

    Clive Maxfield Strange modes of transport and other "stuff"

    Someone just pointed me at a YouTube video that claims to show the world's first e-powered multicopter flight...

     

    Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut