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| 2012-02-03 | Silicon photonics: The solution to crosstalk? Panellists at DesignCon 2012 discuss solutions for measuring the effects of crosstalk on a communications chip and methods to minimise crosstalk. |
| 2012-01-31 | Avago, TI showcase 100GE solutions Avago and TI demonstrate new components that claim to enable boards and cables to higher data rates over longer distances for less power and cost, enabling systems using 100G Ethernet and 10+Gbit/s interfaces. |
| 2012-01-27 | FPGAs tout power, speed, size enhancements Lattice's Low Power, High Speed, and Mini Package additions to its LatticeECP3 FPGA family targeted at consumer, communication and video applications. |
| 2011-12-05 | ASIC Serdes achieves CEI-28G-VSR compliance ASIC Serdes achieves CEI-28G-VSR compliance |
| 2011-12-02 | Clocking, interface IP available in 28nm Analog Bits reveals integrated clocking and interface IP including PLL, DLL, SERDES, DDR3 I/Os, TCAM high performance memories, and on-die thermometer on 28nm process technologies. |
| 2011-10-24 | Implement transceiver with minimal protocol Learn how TLK2711-SP can be implemented using a minimal protocol with various levels of additional complexity for added features. |
| 2011-08-25 | Accessing 16bit I2C register addresses Know how to access 16bit register addresses through the gigabit multimedia serial link (GMSL) SerDes' remote-side I2C interface. |
| 2011-06-29 | Calculate CCEN duration for MAXX9257/MAX9258 programmable SerDes chipset Calculate CCEN duration for MAXX9257/MAX9258 programmable SerDes chipset |
| 2011-05-23 | Design flip-chip packages with integrated USB 3.0 Learn about the use of IE3D to design a four-layer package that has a USB 3.0 interface. |
| 2011-03-22 | Serdes IP powers next-gen flat panel displays Serdes IP powers next-gen flat panel displays |
| 2011-02-10 | 40nm SerDes IP supports multiple protocols 40nm SerDes IP supports multiple protocols |
| 2011-02-03 | Avago uses LeCroy oscilloscope to demo 30Gbit/s Avago Technologies uses LeCroy's WaveMaster 8 Zi-A oscilloscope to demonstrate 30Gbit/s performance with its Serialiser/Deserialiser (SerDes) core in 28nm process technology at DesignCon. |
| 2010-08-12 | Trio team on wireless SerDes for LTE, 4G market Trio team on wireless SerDes for LTE, 4G market |
| 2010-07-06 | GMSL line-fault detection This application note describes an easy way to detect serial-link line faults (e.g. line shorts) in Serdes applications. |
| 2010-06-21 | Serdes chipset improves driver safety Serdes chipset improves driver safety |
| 2010-06-15 | Serdes packs zero-latency control channel Serdes packs zero-latency control channel |
| 2010-06-01 | SerDes set implements bidirectional digital video SerDes set implements bidirectional digital video |
| 2010-05-17 | Moving to a discrete Serdes solution for 4G Moving to a discrete Serdes solution for 4G |
| 2010-04-20 | A/V clock generator eliminates PLL tweaking National Semiconductor debuts a triple-rate audio/video clock generator, the LMH1983 that replaces three external PLLs, voltage-controlled crystal oscillators and loop filters to simplify design and reduces BOM cost. |
| 2010-04-05 | Using a low-cost CMOS oscillator as a reference clock for Serdes applications Using a low-cost CMOS oscillator as a reference clock for Serdes applications |
| 2010-03-17 | TLK313x CPRI multi-hop performance with the CDCM7005 clock jitter cleaner Laboratory measurements were performed to determine the impact of reference clock phase noise on the performance of the TLK313x serdes devices in a CPRI multi-hop configuration. |
| 2010-02-26 | 40nm process tech PCIe 3.0 switches to be sampled PLX Technology Inc. will demo PCIe Gen 3 silicon made in 40nm process technology that uses Serdes with decision feedback equalisation. |
| 2010-02-16 | Moving to a discrete Serdes solution for 4G Moving to a discrete Serdes solution for 4G |
| 2010-02-11 | Internet-driven society demands limit beyond 10GbE Electronics engineers are hitting the limits of their tools and techniques—and perhaps even physics—to keep pace with the rapidly-expanding needs of an Internet-driven society. |
| 2009-12-30 | Implementing the scalable Serdes framer interface (SFI-S) protocol in Stratix IV GT devices Implementing the scalable Serdes framer interface (SFI-S) protocol in Stratix IV GT devices |
| 2009-12-29 | Implementing the Serdes Framer interface level 5 (SFI-5.1) protocol in Stratix IV devices Implementing the Serdes Framer interface level 5 (SFI-5.1) protocol in Stratix IV devices |
| 2009-10-13 | Using SPI read and write with the µSerdes FIN324C Using SPI read and write with the µSerdes FIN324C |
| 2009-08-18 | Equaliser optimises high-speed signal routing Maxim Integrated Products has launched the MAX3986, a 1Gbps to 10.3Gbps, quad linear equaliser for copper interconnects. |
| 2009-07-21 | Intro to LatticeSC Serdes jitter Intro to LatticeSC Serdes jitter |
| 2009-06-23 | PRBS mode setup for MAX9257/MAX9258 eval kit This application note details how to use the internal BER testing (BERT) feature of the MAX9257/MAX9258 Serdes in its pseudorandom bit sequence (PRBS) mode. |
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