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| 2012-04-25 | Mentor's verification platform aids SoC design Mentor's verification platform aids SoC design |
| 2011-10-19 | LG Electronics adopts Synopsys' CustomSim LG Electronics adopts Synopsys' CustomSim FastSPICE for mixed-signal SoC verification to accelerate verification of its analogue IP and SoCs by an average of 10x over previous solutions. |
| 2011-04-25 | Mixed-signal verification tool automates regression Mixed-signal verification tool automates regression |
| 2011-03-21 | Verification IP portal aids design community Verification IP portal aids design community |
| 2011-03-15 | What makes an optimal SOC verification strategy What makes an optimal SOC verification strategy |
| 2011-03-07 | Synopsys, Xilinx unveil SoC design manual Synopsys, Xilinx unveil SoC design manual |
| 2011-01-31 | Synthesis tool eases SoC design verification Synthesis tool eases SoC design verification |
| 2010-12-20 | Verification kit optimised for SoC interface protocols Verification kit optimised for SoC interface protocols |
| 2010-12-16 | Microsemi chooses Sibridge's verification IP Microsemi chooses Sibridge's verification IP |
| 2010-11-29 | Mentor ties with R&S on wireless SoC debug platform Mentor ties with R&S on wireless SoC debug platform |
| 2010-05-19 | Open integration platform ups SoC realisation Open integration platform ups SoC realisation |
| 2010-05-11 | Tool enables full-chip assertion synthesis EDA start-up NextOp rolls out initial product, dubbed BugScope, a full-chip assertion synthesis product that automatically generate functional coverage properties from testbench and RTL. |
| 2008-04-12 | Multi-language verification for multi-site projects, Part 2 Multi-language verification for multi-site projects, Part 2 |
| 2008-02-18 | Multi-language SoC verification for multi-site projects Multi-language SoC verification for multi-site projects |
| 2008-11-25 | Accelerate functional verification Accelerate functional verification |
| 2008-10-31 | Calypto, Forte team-up advances SystemC flow The three-year collaboration of Calypto and Forte has advanced SystemC to cover verification and implementation of multimedia SoCs. |
| 2008-10-24 | Accelerating verification closure for complex SoCs, IPs Accelerating verification closure for complex SoCs, IPs |
| 2008-10-16 | Grasp SystemVerilog testbench debug, analysis The task of chip verification is becoming ever so complex as silicon shrinks and SoC designs grow larger. SystemVerilog addresses this challenge by serving as a platform for enabling advanced methodologies and automation. |
| 2007-11-05 | Design with Verification: Not an Oxymoron Design with Verification: Not an Oxymoron |
| 2007-11-01 | Rising software complexity dictates FPGA-based prototyping The growing use of multicores is adding to the tremendous growth of software used in an ASIC or SoC, further increasing their complexity. What does this trend toward increased software mean for the overall design process? |
| 2007-10-10 | Oki adopts Synopsys' SystemVerilog for verification Oki adopts Synopsys' SystemVerilog for verification |
| 2007-08-29 | Cadence verification kit targets wireless and consumer SoC design Cadence verification kit targets wireless and consumer SoC design |
| 2007-05-03 | Mentor-Anite platform targets handheld devices Anite is partnering with EDA group Mentor Graphics on a complete verification platform that will provide an integrated and efficient set up to verify base band SoC designs. |
| 2007-04-18 | Simulate embedded hardware acceleration The HES system provides solutions for the different verification stages, including hardware acceleration simulation, SoC HW/SW acceleration co-verification and hardware prototype verification. |
| 2007-03-28 | Use timing-accurate system-level models A virtual system prototype provides a software simulation-based model of the electronic system that allows design teams to improve design productivity, reduce time-to-market and decrease risk. |
| 2007-03-15 | Cadence solution enables Taiwan's first 65nm IC design Cadence Design announced that Global Unichip was the first Taiwan-based design company to complete a successful tape-out of a 65nm device with the use of Cadence Low-Power Solution and SoC Encounter GXL RTL-to-GDSII system. |
| 2007-02-01 | Verification box exceeds 200MHz speeds, ASIC gates Verification box exceeds 200MHz speeds, ASIC gates |
| 2007-01-10 | Renesas adopts Synopsys' VCS verification, VMM method Renesas adopts Synopsys' VCS verification, VMM method |
| 2006-12-21 | Chip designers satisfied with IC verification environments Chip designers satisfied with IC verification environments |
| 2006-06-20 | Renesas Vietnam selects Synopsys as EDA provider Synopsys has announced that Renesas has chosen it as the EDA provider for SoC design. |
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