| Cadence, Mentor launch OVM
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2008-01-11 |
| Cadence and Mentor have launched the OVM based on IEEE Std. 1800-2005 SystemVerilog standard, which they claim as the industry's first open, language interoperable, SystemVerilog verification methodology. |
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| OSCI releases transaction-level modeling standard
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2007-12-05 |
| OSCI has announced the release of the new transaction-level modeling standard that enables model interoperability and reuse at the transaction level, providing an essential framework for ESL design. |
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| Synplicity joins Xilinx ESL design ecosystem
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2007-11-28 |
| Synplicity has announced that the addition of its Synplify DSP software to the Xilinx ESL design ecosystem has underscored the commitment of Xilinx towards driving tech innovations and solutions that promote high-level, ESL design. |
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| Synplicity, Lattice deliver ESL synthesis flow for DSP
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2007-11-08 |
| Synplicity and Lattice Semiconductor have expanded their relationship to include delivery of a highly optimised, non-proprietary ESL synthesis flow for DSP design. |
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| 45nm designs face I/O planning, placement challenges
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2007-11-01 |
| With the move to the 45nm process node, more chip designs are going to be pad-limited, and die sizes will be directly affected by how I/Os are placed and sequenced efficiently.. |
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| Cadence, Mentor promote OVM
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2007-10-16 |
| Cadence and Mentor have joined forces to offer an OVM rooted in IEEE 1800 with transaction-level modeling support that is interoperable among EDA tools and that supports interoperable VIP. |
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| Oki adopts Synopsys' SystemVerilog for verification
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2007-10-10 |
| Oki has identified several factors contributing to the rapid adoption of their advanced verification services that include the combination of SystemVerilog, the VMM and verification IP from the VCS Verification Library |
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| Structured ASICs- an attractive option for custom IC design
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2007-09-03 |
| Given the increasing NRE charges and long design schedules associated with deep-submicron standard-cell ASICs, the use of structured ASICs for custom IC design is an increasingly attractive option.. |
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| Cadence, Mentor team to standardise OVM
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2007-08-22 |
| Cadence and Mentor Graphics have partnered to standardise on OVM that promises to deliver a tool-independent solution for designers and verification engineers that promotes data portability and interoperability. |
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| TSMC bridges design-manufacturing gap
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2007-07-16 |
| TSMC has unveiled Reference Flow 8.0 design methodology that addresses the issue of moving expensive 45nm designs into production without circuit failures, mask re-spins or other costly problems. |
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| UMC, ARM partnership offers 65nm SOI solutions
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2007-06-12 |
| The successful tape-out of a test chip built with ARM SOI libraries on UMC's 65nm SOI process represents the next step towards mainstream adoption of nanometer SOI technology. |
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| TSMC denies its entry into IP business
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2007-05-22 |
| TSMC's claim that it is not in the IP licensing business would carry weight only if the company did all its support engineering for free and made the results freely available to second and third parties |
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| ARM appoints new MD, India ops
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2007-04-25 |
| ARM has announced the appointment of Anil Gupta as managing director, India operations. |
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| NSC, IPextreme sign IP distribution agreement
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2007-02-22 |
| IPextreme Inc. and National Semiconductor Corp. have signed an intellectual property (IP) distribution agreement |
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| IP chip expands use of MIPS cores
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2007-01-16 |
| Fabless ASIC provider Open-Silicon Inc. has expanded its intellectual property (IP) chip and library offerings by signing a deal with MIPS Technologies Inc. The pact with MIPS allows Open-Silicon to offer the MIPS32 24Kc Pro processor core for use in ASIC and SoC designs |
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| Magma, UMC complete 65nm library suite
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2007-01-08 |
| Magma Design Automation announced that United Microelectronics Corp. (UMC) has characterised its internally developed libraries for 65nm and smaller process geometries using Magma's SiliconSmart. |
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| Fujitsu adopts ARM Velocity's standard cells
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2006-12-13 |
| ARM's Velocity PHY for PCIe Gen-2 and the Advantage v2.0 standard cell library has been adopted by Fujitsu Ltd on its CS200 HP 65nm platform. The agreement enables Fujitsu to offer foundry customers access to ARM physical IP, which provides an optimal design solution for advanced LSI development |
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| Pextra joins In-Sequence tech program
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2006-12-07 |
| Sequence Design has announced that Pextra Corp. has joined its In-Sequence Technology Partner Program, promoting EDA interoperability and advanced design methodologies. |
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| IBM, Chartered, Samsung license ARM's 45nm tech
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2006-10-31 |
| Common Platform technology business partners IBM, Chartered Semiconductor Manufacturing and Samsung Electronics Co. Ltd have licensed ARM's proprietary products for 45nm LP process technology. |
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| Bluespec, Satyam Computer alliance to expand presence in India
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2006-10-18 |
| Bluespec Inc. has signed a services agreement with Satyam Computer Services Ltd, which will provide Bluespec with intellectual property (IP) development and services, customer product support and product quality assurance (QA) capabilities |
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| Fujitsu signs agreement to distribute Tensilica processor cores
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2006-09-15 |
| Fujitsu Microelectronics America Inc. has signed an agreement to distribute Tensilica Inc.'s Diamond Standard processor cores as part of Fujitsu's ASIC intellectual property (IP) offering |
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| Cadence, Mentor battle over high-speed IC design
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2006-09-01 |
| Lack of standards for simulating chip interconnects as they scale up to 5Gbps and beyond has pitted Cadence and Mentor in fight for competing solutions. |
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| IBM, Chartered, Infineon, Samsung announce first ICs on 45nm
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2006-08-31 |
| IBM, Chartered Semiconductor, Infineon Technologies and Samsung disclosed that they have developed their first functional chips based on a low-power, 45nm process technology. |
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| Cadence, Magma, Extreme DA to develop industry standard library format
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2006-07-28 |
| Cadence Design Systems, Magma Design Automation and Extreme DA, with support from ARM, Virage Logic Corp. and Altos Design Automation, have announced their collaboration to accelerate the creation of a standard statistical analysis library format under the Open Modelling Coalition of Si2 |
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| Summit Design launches IP initiative
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2006-07-13 |
| Summit Design Inc. has launched its Intellectual Property (IP) Initiative, which aims to address IP interoperability issues at the system level |
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| Renesas Vietnam selects Synopsys as EDA provider
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2006-06-20 |
| Synopsys has announced that Renesas has chosen it as the EDA provider for SoC design. |
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| EVE selects eInfochips as design services partner
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2006-05-02 |
| EVE has selected eInfochips for expanding and complement the internally-developed synthesisable transactor library for EVE's ZeBu emulation platform |
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| ARM, TSMC enter long-term IP agreement for 65nm, 45nm
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2006-04-24 |
| ARM and TSMC are extending their long-term relationship to development of a new suite of ARM Advantage products in support of TSMC's 65nm and 45nm G processes. |
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| Synopsys announces first Verification Library
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2006-03-27 |
| Synopsys has announced its VCS Verification Library, which is first to support testbenches created using IEEE Std 1800-2005 SystemVerilog and the coverage-driven methodology |
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| Xilinx, CMC increase IP development in India
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2006-03-03 |
| Xilinx has revealed that its India development centre in Hyderabad has delivered 24 IP cores since its establishment in February 2004 |
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