| Wipro joins PFI, offers low-power design
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2008-09-11 |
| Wipro is now a member of Power Forward Initiative, and is offering CPF-enabled low-power design capabilities. |
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| Socle adopts SpyGlass-DFT product
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2008-09-05 |
| Socle has adopted Atrenta's SpyGlass- DFT product for IP verification and testability hand-off |
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| Synopsys preps for 'techonomic' challenges
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2008-07-01 |
| Synopsys CEO Aart de Geus: I call the challenges "techonomic" because technology and money affect each other. |
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| Engineers demo new verification planning process
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2008-06-18 |
| Two engineers recently demonstrated a formal verification planning process at a conference in India. |
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| Broadcom focus on mobile market, ramp shift to 65nm
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2008-03-17 |
| Broadcom is moving in two directions: entering the cellphone market and ramping the shift to 65nm. |
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| X-FAB adds RF-CMOS options to 0.18µm tech
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2008-01-16 |
| X-FAB has transformed the X-FAB Sarawak, Malaysia, facility into an analogue/mixed-signal (AMS) fab and transferred four complex processes and added a new 0.18 micrometer tech to its line-up. |
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| Cadence, Mentor launch OVM
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2008-01-11 |
| Cadence and Mentor have launched the OVM based on IEEE Std. 1800-2005 SystemVerilog standard, which they claim as the industry's first open, language interoperable, SystemVerilog verification methodology. |
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| AMD, Intel ramp up their SoC capabilites
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2007-12-12 |
| Though both AMD and Intel will continue to design high-end custom microprocessors, increasingly their competition will hinge on how well they assemble chips out of a stock of reusable cores. |
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| OSCI releases transaction-level modeling standard
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2007-12-05 |
| OSCI has announced the release of the new transaction-level modeling standard that enables model interoperability and reuse at the transaction level, providing an essential framework for ESL design |
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| Altera, Synopsys team to offer Nios II for ASIC designs
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2007-11-15 |
| Utilising its core competencies in design-for-reuse, IP packaging methodologies and design flows, Synopsys will provide a configurable, fully synthesizable version of the Altera Nios II processor core optimised for ASIC implementation |
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| IBM pioneers IC wafer reclamation process
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2007-11-05 |
| IBM has pioneered a new IC wafer reclamation process that removes the IP from the wafer surface, making these wafers available either for reuse in internal manufacturing calibration as "monitor wafers" or for sale to the solar cell industry |
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| Dealing with IP at smaller process nodes
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2007-11-01 |
| With the increasing demand for connectivity IP for high-speed serial buses, the IC tech require ultralow-power derivatives of high-performance logic manufacturing processes that enable production of very low-power SoCs for mobile platforms and small form-factor devices |
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| 45nm designs face I/O planning, placement challenges
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2007-11-01 |
| With the move to the 45nm process node, more chip designs are going to be pad-limited, and die sizes will be directly affected by how I/Os are placed and sequenced efficiently.. |
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| Cadence, Mentor promote OVM
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2007-10-16 |
| Cadence and Mentor have joined forces to offer an OVM rooted in IEEE 1800 with transaction-level modeling support that is interoperable among EDA tools and that supports interoperable VIP. |
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| Cadence, Mentor team to standardise OVM
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2007-08-22 |
| Cadence and Mentor Graphics have partnered to standardise on OVM that promises to deliver a tool-independent solution for designers and verification engineers that promotes data portability and interoperability. |
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| Commoditisation threatens ASIC business
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2007-05-02 |
| The tumultuous ASIC business is undergoing a shakeout amid soaring design, verification and mask costs, coupled with the economic realities in the market. |
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| OCP-IP launches NoC benchmarking initiative
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2007-03-08 |
| Providing a way to compare performance, cost, and other features of multi-processor SoC architectures, the Open Core Protocol International Partnership (OCP-IP) is launching a network-on-chip (NoC) benchmarking initiative. The first deliverable is a new white paper that outlines the essential features of an NoC benchmarking environment |
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| ARM, eASIC announce processor IP deal
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2007-01-08 |
| Expanding its product offerings, fabless ASIC house eASIC Corp. has announced a deal with ARM Ltd. The partnership will enable a broad range of users to have access to ARM's 32-bit processor core on a configurable fabric. |
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| IBM, Chartered, Samsung license ARM's 45nm tech
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2006-10-31 |
| Common Platform technology business partners IBM, Chartered Semiconductor Manufacturing and Samsung Electronics Co. Ltd have licensed ARM's proprietary products for 45nm LP process technology. |
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| Power processor brings IBM, Freescale together
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2006-09-01 |
| IBM and Freescale will jointly develop the Power processor architecture. |
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| Denali, Spirit Consortium sign IP-XACT development collaboration
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2006-07-31 |
| Denali Software Inc. has said that it would work with the Spirit Consortium on development of IP-XACT to ensure that the consortium data model is aligned with SystemRDL |
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| Summit Design launches IP initiative
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2006-07-13 |
| Summit Design Inc. has launched its Intellectual Property (IP) Initiative, which aims to address IP interoperability issues at the system level |
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| FSA signs MoU to establish IP trading centre
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2006-06-23 |
| The FSA has signed a memorandum of understanding with three other groups to establish the Greater China Semiconductor Intellectual Property Trading Centre. |
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| Breaking the IC verification barrier
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2006-06-01 |
| Startup OneSpin Solutions believes that it has technology that will usher in an era of IC formal verification. |
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| Saifun Semi adopts Cadence AMS kit
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2006-04-28 |
| Cadence Design Systems Inc. has announced that Saifun Semiconductors has adopted Cadence's Analog Mixed Signal Methodology Kit. |
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| MindTree Bluetooth protocol supports ADI Blackfin processor
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2006-03-16 |
| MindTree Consulting has announced that its v2.0+ EDR Bluetooth protocol stack and application profiles are delivering wireless capabilities within Analog Devices' Blackfin-based PMP. |
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| Is VoIP over Wireless LAN secure?
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2006-02-21 |
| WLAN IP phones or converged cellular/WLAN phones pose many security problems. Here's how to solve them |
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| QIP metric upgrade may ease IP selection
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2006-02-16 |
| Selecting silicon intellectual property (IP) may get a little easier, as the VSI Alliance has released its QIP Metric 2.0 for free |
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| IP reuse needs a verification strategy
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2005-12-22 |
| The concept of reuse seems simple and easy in theory, but there are a number of obstacles that design and verification teams must address to be successful |
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| IEEE approves SystemC standard based on SystemC 2.1
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2005-12-14 |
| IEEE has said that it has approved the SystemC electronic design language standard. IEEE standardization may help bring SystemC into more widespread use and pave the way for further support from commercial EDA tools. |
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Strange modes of transport and other "stuff"
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