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EE Times India - total search 316 articles sort by date sort by relevance
Rising software complexity dictates FPGA-based prototyping 2007-11-01
The growing use of multicores is adding to the tremendous growth of software used in an ASIC or SoC, further increasing their complexity. What does this trend toward increased software mean for the overall design process?  
Dealing with IP at smaller process nodes 2007-11-01
With the increasing demand for connectivity IP for high-speed serial buses, the IC tech require ultralow-power derivatives of high-performance logic manufacturing processes that enable production of very low-power SoCs for mobile platforms and small form-factor devices.  
Addressing the challenges of process node transition 2007-11-01
In the transition to 45nm, reaching node availability, readiness and adoption has become significantly more complex  
Full- and Hi-Speed USB 2.0 device controller debuts 2007-10-09
Altera Corp. has introduced a complete USB 2.0 Hi-/Full-Speed device controller solution that consists of a soft IP core, software and class drivers, and SLS' Snap-On PHY daughtercards.  
Agilent develops 3D EM stimulator 2007-10-04
Agilent has developed a planar 3D electromagnetic simulator designed to expand the accuracy and range of passive circuit libraries, including parasitic models and entire circuits.  
Researchers display future PC interface tech 2007-10-01
Researchers showcased future technologies of computer interfaces and graphics including a locomotion interface for virtual environments, a virtual video recording system and multitouch displays among others.  
Key specs for SRD transceivers 2007-10-01
As low-power wireless technologies compete for dominance in replacing wires and cable in home networking, automation and sensor systems, the importance of short-range radio transceivers has grown.  
Tower offers to support India chip manufacturing groups 2007-09-28
Israeli fab is in talks with SemIndia and HSMC to bring to their cooperation an offering which includes special areas such as CMOS sensors found in mobile phones, automotive and medical apps.  
Chipmakers explore virtual world market 2007-09-25
Intel is determined to be among the first to rally the industry around the devt of standards and tech that would one day make it possible to move user-generated content from one virtual world to another.  
Firms address 65nm FPGA design verification 2007-09-24
Xilinx has partnered with Cadence, Mentor and Synopsys to define and implement new verification flows for ultrahigh-density designs of 65nm FPGAs and new emerging FPGA architectures.  
Chip makers, EDA vendors set up DFM coalition 2007-09-21
The Silicon Integration Initiative (Si2) has announced that top chip makers and EDA tool vendors have established a coalition to add DFM parameters to existing design flow.  
IIT researchers develop new digital module testing tech 2007-09-20
A team of researchers at the IIT, Kharagpur have developed new approach for testing digital modules embedded in mixed-signal VLSI circuits.  
Synopsys, SiSoft develop signal integrity analysis solution 2007-09-17
Synopsys and SiSoft have integrated SiSoft's Quantum-SI tool and Synopsys' HSPICE simulation solution to deliver robust timing and signal integrity analysis for package and PCB design  
AMD, Qimonda launch joint chip simulation project 2007-09-06
AMD and Qimonda have launched a joint chip simulation project that includes modeling and simulation at the physical level and refers to materials, architectures and manufacturing processes  
Using emulation for system level sign-off 2007-09-04
Today EDA vendors are hard at work extending the range of tools supporting sign-off to meet the changing landscape introduced with the nanometre age.  
ESC, EDA&T-Taiwan showcased Asia's faster uptake on software, IP 2007-08-29
The ESC-Taiwan and EDA&T-Taiwan shows seemed a testament to Asia's faster uptake on software and IP industries, given semiconductor industry's evolution and software?s increasing stakes in it.  
Software, IP solutions dominate ESC-Taiwan, EDA&T-Taiwan 2007-08-29
Software and IP solutions took the centerstage at this year's ESC-Taiwan and EDA&T-Taiwan show in Taipei last August 23-24.  
Cadence, Mentor team to standardise OVM 2007-08-22
Cadence and Mentor Graphics have partnered to standardise on OVM that promises to deliver a tool-independent solution for designers and verification engineers that promotes data portability and interoperability.  
Xilinx, EDA giants address 65nm FPGA verification 2007-08-17
Xilinx has collaborated with three major EDA companies to define and implement new verification flows to maximise productivity for ultrahigh-density designs targeting today's 65nm FPGAs.  
Cadence, SMIC jointly develop RF design solution 2007-08-06
Cadence has joined hands with SMIC to develop RF design solution that will help chip designers in China to design and deliver high-quality RF devices.  
UK trade dept awards CDT to develop EDA for organic apps 2007-07-19
A consortium of CDT and Silvaco has been granted Rs.2.04 crore ($500,000) to extend the use of EDA software to organic semiconductor materials and accelerate the dvlt of low-cost fabrication techniques for organic displays.  
Multicore shakes up EDA industry 2007-07-16
The EDA vendors accept that though multi-core platforms provide much-needed compute power as transistor counts soar at 65nm and below, but they can prove a cause of concern for legacy apps that could be difficult or even impossible to parallelise.  
SoftMEM's tools add MEMS to EDA software 2007-07-03
SoftMEM's toolsets, when integrated with existing EDA tool sets, enables EEs to co-design electronics-with-MEMS chips without having to have the deep MEMS knowledge of a guru.  
TSMC, Cadence partners on 65nm wireless design flow 2007-06-28
Cadence has collaborated with TSMC to produce a new TSMC 65nm RF process design kit (PDK) compatible with the new Cadence Virtuoso custom design platform.  
BEL delivers spacecraft components to ISRO 2007-06-19
BEL has delivered two Flight Model Travelling Wave Tubes (TWTs) that are Space-Qualified Components used on board Communication Satellites to ISRO.  
Renesas develops SOI SRAM tech for 32nm, beyond 2007-06-14
Renesas is hoping to extend operation margins by controlling the body potential of SRAM component transistors individually in line with SRAM operations such as writes and reads.  
UMC, ARM partnership offers 65nm SOI solutions 2007-06-12
The successful tape-out of a test chip built with ARM SOI libraries on UMC's 65nm SOI process represents the next step towards mainstream adoption of nanometer SOI technology.  
Agilent expands design platform tech 2007-06-08
Agilent Technologies is planning to increase investments in RF/microwave design and simulation technologies to provide a full spectrum of software tools to designers  
IC designers analyse DFM tools 2007-06-01
IC design experts believed that DFM is best addressed through design rules, preverified blocks and improved standard-cell libraries, said the experts.  
Mentor, UMC address AMS needs 2007-05-30
Mentor Graphics and UMC have collaborated to develop a mixed-signal design flow that includes an integrated environment for design capture, data management and verification.  


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Clive Maxfield Strange modes of transport and other "stuff"

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