| Partnership simplifies FPGA, PCB design collaboration
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2007-05-25 |
| Zuken, Aldec partnership to help facilitate collaboration between FPGA and PCB designers, would allow layout engineers to perform pin swaps that concurrently update all PCB and FPGA design data. |
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| Cosmic backs Asia foray with IP integration support
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2007-05-16 |
| During the past six months, Cosmic Circuits Pvt. Ltd has been rapidly expanding its presence in key markets in Asia and the Middle East through its partner networks. |
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| Chandran Nair explains NI's strategy for test
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2007-05-16 |
| Chandran Nair, managing director of NI Southeast Asia, talks about how the company has moved from the test and measurement domain to the embedded turf. |
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| Open constraint format triggers EDA standards debate
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2007-05-09 |
| The recent Synopsys Interoperability Forum may have offered the public the first view of an open analogue constraint format, which could be a beginning of a news standards effort. |
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| EU project's embedded roadmap centres on multi-core, compilation
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2007-05-04 |
| HiPEAC, a project on high performance embedded applications and compilers, has produced a guide to the major challenges facing embedded applications for the next several years. |
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| Cell-mainframe hybrid to handle virtual world simulations
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2007-05-02 |
| IBM and Hoplon Infotainment collaborate to integrate the Cell Broadband Engine in mainframe to create a hybrid capable of handling a new generation of "virtual world" applications, such as the 3D Internet. |
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| Cell-mainframe hybrid handles 3D simulations
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2007-04-30 |
| IBM and Hoplon Infotainment collaborate to integrate the Cell Broadband Engine in mainframe to create a hybrid capable of handling a new generation of "virtual world" applications, such as the 3D Internet. |
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| Phase filter implements AJC technology; reduces power, silicon area
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2007-04-19 |
| Results of FME and Toric's embedded jitter project were revealed. |
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| FPGA use in HPCs faces bottleneck problems
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2007-04-02 |
| Current FPGA synthesis, placement and routing tools are written for hardware designers, not software programmers. A new generation of ESL C-language compilers is attempting to bridge the gap. |
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| Planning the verification process with SystemVerilog
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2007-03-23 |
| The best way for the verification team to match the automatic tests with their corresponding design features is via functional coverage metrics. |
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| SMIC teams up with Cascade, Agilent for RFIC design, test
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2007-03-20 |
| SMIC announced separate partnerships with Cascade Microtech and Agilent Technologies to provide RFIC services for RF design engineers in greater China. |
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| SystemVerilog fails to deliver on design
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2007-02-21 |
| SystemVerilog is widely applied to verification, however, design use lags due to concerns about tool support. |
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| Circuit designers take control over layout parameters
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2007-02-16 |
| To help schematic simulation closely match post-layout simulation, the designer must predict how schematic devices will be combined in the layout and gain control over the parameters used to model the layout characteristics |
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| VERTIGO to check on TLM, RTL standards
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2007-02-08 |
| The Commission of the European Communities within the I ST area has launched a project to bridge the gap between system-level modelling and verification performed at the transactional level and the traditional RTL signoff description. |
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| Leveraging IP for market ownership
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2007-02-08 |
| Tensilica's senior vice president talks to EE Times India about India's needs to develop and leverage IP, in order to move its present design services model up the design chain. |
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| Agilent to set up R&D modelling centre
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2007-02-08 |
| Agilent Technologies Inc. has announced its plans to expand its investment in its IC-CAP device modelling software and establish a new R&D modelling centre in Asia. |
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| Spansion joins Denali's software program
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2007-02-07 |
| To further leverage its position in the industry, Spansion has joined Denali Software's MVP. This provides chip designers with high-quality simulation models and other engineering resources to efficiently deploy Spansion flash devices into electronic designs |
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| Engineers face thermal challenges on designs
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2007-02-05 |
| Designers are struggling to keep their cool while facing thermal challenges in all designs—chips, boards, modules and systems, with increasing chip speed and density. |
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| Mentor, EVE settle patent infringement case
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2007-01-15 |
| Mentor Graphics Corp. and emulation provider EVE Corp. have settled a previously unpublicised patent infringement lawsuit, disclosed the two companies. The legal action was pending in the United States District Court of Oregon. |
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| Cadence incisive formal verifier selected for Ubicom's logic design team
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2007-01-08 |
| Cadence Design Systems Inc. has announced that Ubicom has incorporated the Cadence Incisive Formal Verifier solution into its overall design flow. |
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| Forte Design Systems announces new appointments
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2006-12-27 |
| Forte Design Systems has named Sean Dart to serve as president and CEO. Forte also announced that Brett Cline has been promoted to vice president of sales and marketing. |
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| Mentor to focus on R&D centres in India
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2006-12-21 |
| Mentor Graphics will strengthen its focus on building centres of excellence within its India R&D operations. Its R&D centres in India, located in Hyderabad and Noida, concentrate on developing technology as well as products, in distinct areas. |
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| Calypto hosts seminar on ESL methods for RTL design
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2006-12-20 |
| Calypto Design Systems (India) Pvt. Ltd hosted a half-day seminar titled 'ESL methods for RTL design and verification' in November 2006, with its distributor CMR Design Automation. |
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| Tokyo university, Taiwan firms finish work on 512-core chip
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2006-12-14 |
| The University of Tokyo recently finished up work on a 512 core chip in collaboration with TSMC. and Alchip Technologies, a fabless ASIC company also from Taiwan. The chip, called Sing, is part of the larger Grape DR project to create the next-generation of supercomputers, capable of 2,000 trillion transactions per second. |
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| Cadence CEO discusses emerging trends in semicon design
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2006-12-06 |
| Michael J. Fister, president and CEO, Cadence Design Systems Inc., says that's as design complexity across custom ICs, digital ICs, PCB and packaging increases, a holistic level of capabilities are now required from semiconductor design and EDA companies alike. |
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| Taiwan's CIC licenses ARM processors
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2006-12-05 |
| ARM has announced that the National Chip Implementation Centre (CIC), an organisation that promotes IC design and innovation in Taiwan, has licensed the ARM7TDMI and ARM926EJ-S processors. |
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| VLSI design conference to focus on nano-electronics
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2006-11-16 |
| The 20th international conference on VLSI design and the 6th international conference on embedded systems will be held from January 6-10, 2007 at the NIMHANS Convention Centre, Bangalore. |
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| Revised VHDL spec boosts IP security
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2006-11-16 |
| The Accellera standards organisation has approved a revised version of the VHDL specification, marking a huge step forward for the design language. Pending IEEE approval, the revision will bring Property Specification Language (PSL) assertions into VHDL and will add capabilities for IP encryption. |
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| Banpil sends 10Gbps signals 1.5m
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2006-11-15 |
| Banpil Photonics Inc. has demonstrated a way to send 10Gbps signals 1.5m across a standard pc-board without using power-hogging techniques to amplify the signal. The demo included sending 20Gbps signals one metre between chips. |
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| ARM appoints Tata Elxsi as first approved design centre
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2006-11-13 |
| Tata Elxsi Ltd has been appointed as the first approved design centre of the UK-based ARM Embedded Technologies Ltd to develop software and embedded applications for silicon vendors. |
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