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EE Times India - total search 316 articles sort by date sort by relevance
Partnership simplifies FPGA, PCB design collaboration 2007-05-25
Zuken, Aldec partnership to help facilitate collaboration between FPGA and PCB designers, would allow layout engineers to perform pin swaps that concurrently update all PCB and FPGA design data.  
Cosmic backs Asia foray with IP integration support 2007-05-16
During the past six months, Cosmic Circuits Pvt. Ltd has been rapidly expanding its presence in key markets in Asia and the Middle East through its partner networks.  
Chandran Nair explains NI's strategy for test 2007-05-16
Chandran Nair, managing director of NI Southeast Asia, talks about how the company has moved from the test and measurement domain to the embedded turf.  
Open constraint format triggers EDA standards debate 2007-05-09
The recent Synopsys Interoperability Forum may have offered the public the first view of an open analogue constraint format, which could be a beginning of a news standards effort.  
EU project's embedded roadmap centres on multi-core, compilation 2007-05-04
HiPEAC, a project on high performance embedded applications and compilers, has produced a guide to the major challenges facing embedded applications for the next several years.  
Cell-mainframe hybrid to handle virtual world simulations 2007-05-02
IBM and Hoplon Infotainment collaborate to integrate the Cell Broadband Engine in mainframe to create a hybrid capable of handling a new generation of "virtual world" applications, such as the 3D Internet.  
Cell-mainframe hybrid handles 3D simulations 2007-04-30
IBM and Hoplon Infotainment collaborate to integrate the Cell Broadband Engine in mainframe to create a hybrid capable of handling a new generation of "virtual world" applications, such as the 3D Internet.  
Phase filter implements AJC technology; reduces power, silicon area 2007-04-19
Results of FME and Toric's embedded jitter project were revealed.  
FPGA use in HPCs faces bottleneck problems 2007-04-02
Current FPGA synthesis, placement and routing tools are written for hardware designers, not software programmers. A new generation of ESL C-language compilers is attempting to bridge the gap.  
Planning the verification process with SystemVerilog 2007-03-23
The best way for the verification team to match the automatic tests with their corresponding design features is via functional coverage metrics.  
SMIC teams up with Cascade, Agilent for RFIC design, test 2007-03-20
SMIC announced separate partnerships with Cascade Microtech and Agilent Technologies to provide RFIC services for RF design engineers in greater China.  
SystemVerilog fails to deliver on design 2007-02-21
SystemVerilog is widely applied to verification, however, design use lags due to concerns about tool support.  
Circuit designers take control over layout parameters 2007-02-16
To help schematic simulation closely match post-layout simulation, the designer must predict how schematic devices will be combined in the layout and gain control over the parameters used to model the layout characteristics  
VERTIGO to check on TLM, RTL standards 2007-02-08
The Commission of the European Communities within the I ST area has launched a project to bridge the gap between system-level modelling and verification performed at the transactional level and the traditional RTL signoff description.  
Leveraging IP for market ownership 2007-02-08
Tensilica's senior vice president talks to EE Times India about India's needs to develop and leverage IP, in order to move its present design services model up the design chain.  
Agilent to set up R&D modelling centre 2007-02-08
Agilent Technologies Inc. has announced its plans to expand its investment in its IC-CAP device modelling software and establish a new R&D modelling centre in Asia.  
Spansion joins Denali's software program 2007-02-07
To further leverage its position in the industry, Spansion has joined Denali Software's MVP. This provides chip designers with high-quality simulation models and other engineering resources to efficiently deploy Spansion flash devices into electronic designs  
Engineers face thermal challenges on designs 2007-02-05
Designers are struggling to keep their cool while facing thermal challenges in all designs—chips, boards, modules and systems, with increasing chip speed and density.  
Mentor, EVE settle patent infringement case 2007-01-15
Mentor Graphics Corp. and emulation provider EVE Corp. have settled a previously unpublicised patent infringement lawsuit, disclosed the two companies. The legal action was pending in the United States District Court of Oregon.  
Cadence incisive formal verifier selected for Ubicom's logic design team 2007-01-08
Cadence Design Systems Inc. has announced that Ubicom has incorporated the Cadence Incisive Formal Verifier solution into its overall design flow.  
Forte Design Systems announces new appointments 2006-12-27
Forte Design Systems has named Sean Dart to serve as president and CEO. Forte also announced that Brett Cline has been promoted to vice president of sales and marketing.  
Mentor to focus on R&D centres in India 2006-12-21
Mentor Graphics will strengthen its focus on building centres of excellence within its India R&D operations. Its R&D centres in India, located in Hyderabad and Noida, concentrate on developing technology as well as products, in distinct areas.  
Calypto hosts seminar on ESL methods for RTL design 2006-12-20
Calypto Design Systems (India) Pvt. Ltd hosted a half-day seminar titled 'ESL methods for RTL design and verification' in November 2006, with its distributor CMR Design Automation.  
Tokyo university, Taiwan firms finish work on 512-core chip 2006-12-14
The University of Tokyo recently finished up work on a 512 core chip in collaboration with TSMC. and Alchip Technologies, a fabless ASIC company also from Taiwan. The chip, called Sing, is part of the larger Grape DR project to create the next-generation of supercomputers, capable of 2,000 trillion transactions per second.  
Cadence CEO discusses emerging trends in semicon design 2006-12-06
Michael J. Fister, president and CEO, Cadence Design Systems Inc., says that's as design complexity across custom ICs, digital ICs, PCB and packaging increases, a holistic level of capabilities are now required from semiconductor design and EDA companies alike.  
Taiwan's CIC licenses ARM processors 2006-12-05
ARM has announced that the National Chip Implementation Centre (CIC), an organisation that promotes IC design and innovation in Taiwan, has licensed the ARM7TDMI and ARM926EJ-S processors.  
VLSI design conference to focus on nano-electronics 2006-11-16
The 20th international conference on VLSI design and the 6th international conference on embedded systems will be held from January 6-10, 2007 at the NIMHANS Convention Centre, Bangalore.  
Revised VHDL spec boosts IP security 2006-11-16
The Accellera standards organisation has approved a revised version of the VHDL specification, marking a huge step forward for the design language. Pending IEEE approval, the revision will bring Property Specification Language (PSL) assertions into VHDL and will add capabilities for IP encryption.  
Banpil sends 10Gbps signals 1.5m 2006-11-15
Banpil Photonics Inc. has demonstrated a way to send 10Gbps signals 1.5m across a standard pc-board without using power-hogging techniques to amplify the signal. The demo included sending 20Gbps signals one metre between chips.  
ARM appoints Tata Elxsi as first approved design centre 2006-11-13
Tata Elxsi Ltd has been appointed as the first approved design centre of the UK-based ARM Embedded Technologies Ltd to develop software and embedded applications for silicon vendors.  


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