| Cadence, Mentor launch OVM
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2008-01-11 |
| Cadence and Mentor have launched the OVM based on IEEE Std. 1800-2005 SystemVerilog standard, which they claim as the industry's first open, language interoperable, SystemVerilog verification methodology |
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| Success story of an APAC EDA player
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2008-01-02 |
| The hardware capabilities of Taiwan's high-tech industry are well known. However, the industry is relatively weak in its software capability. Meanwhile, in the semiconductor sector, the three biggest EDA suppliers hold about 90% of the market. |
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| India chip designers prepare for business surge
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2007-12-28 |
| Despite an expected weakening of the U.S. economy, top Indian chip designers are now tackling 45nm designs while industry observers expect no let up in demand for Indian design services. |
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| ARM, Esterel to develop software devt tools for safety-critical apps
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2007-12-10 |
| ARM and Esterel Technologies have announced their collaboration on a software development toolchain for safety-critical systems requiring IEC 61508 certification. |
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| OSCI releases transaction-level modeling standard
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2007-12-05 |
| OSCI has announced the release of the new transaction-level modeling standard that enables model interoperability and reuse at the transaction level, providing an essential framework for ESL design. |
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| Fraunhofer to provide design support for Atmel's MCU based chip
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2007-11-29 |
| Atmel Corp. and the Fraunhofer Institute for Integrated Circuits have announced a collaboration to develop SoCs based on Atmel's AT91CAP ARM-based customisable microcontroller. |
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| Synplicity joins Xilinx ESL design ecosystem
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2007-11-28 |
| Synplicity has announced that the addition of its Synplify DSP software to the Xilinx ESL design ecosystem has underscored the commitment of Xilinx towards driving tech innovations and solutions that promote high-level, ESL design. |
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| CoWare platform architect supports Tensilica's 32-bit processor
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2007-11-22 |
| CoWare and Tensilica have announced the integration of Tensilica's Diamond Standard 106Micro, the smallest licensable 32-bit processor core, with CoWare Platform Architect. |
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| Executive: Infineon beefs up its operations in Asia
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2007-11-19 |
| Tuned in to the latest trends in mobile TV, Infineon's tuner system business unit has been developing products according to market needs and has been getting a large slice of the market. |
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| austriamicrosystems expands MPW service for foundry customers
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2007-11-16 |
| austriamicrosystems' business unit Full Service Foundry expands its cost-efficient and speedy ASIC prototyping service, known as MPW or shuttle run, with a more extensive schedule for 2008. |
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| Synplicity, Lattice deliver ESL synthesis flow for DSP
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2007-11-08 |
| Synplicity and Lattice Semiconductor have expanded their relationship to include delivery of a highly optimised, non-proprietary ESL synthesis flow for DSP design. |
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| Rising software complexity dictates FPGA-based prototyping
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2007-11-01 |
| The growing use of multicores is adding to the tremendous growth of software used in an ASIC or SoC, further increasing their complexity. What does this trend toward increased software mean for the overall design process? |
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| 45nm designs face I/O planning, placement challenges
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2007-11-01 |
| With the move to the 45nm process node, more chip designs are going to be pad-limited, and die sizes will be directly affected by how I/Os are placed and sequenced efficiently.. |
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| Researchers discover new Si, Al, Mg isotopes
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2007-10-29 |
| Researchers at Michigan State University's National Superconducting Cyclotron Laboratory have found three never-before-observed isotopes of silicon, aluminum and magnesium. |
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| Program addresses novel IC packaging issues
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2007-10-18 |
| Two research centres have teamed up to establish an industrial affiliation program that targets novel packaging approaches designed to reduce the mechanical stress on the IC after packaging and assembly. |
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| Cadence, Mentor promote OVM
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2007-10-16 |
| Cadence and Mentor have joined forces to offer an OVM rooted in IEEE 1800 with transaction-level modeling support that is interoperable among EDA tools and that supports interoperable VIP. |
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| Oki adopts Synopsys' SystemVerilog for verification
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2007-10-10 |
| Oki has identified several factors contributing to the rapid adoption of their advanced verification services that include the combination of SystemVerilog, the VMM and verification IP from the VCS Verification Library |
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| Synopsys acquires Sandwork Design
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2007-10-05 |
| Synopsys has acquired a provider of analogue and mixed-signal verification solutions to provide a comprehensive environment for verification and debug |
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| Agilent develops 3D EM stimulator
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2007-10-04 |
| Agilent has developed a planar 3D electromagnetic simulator designed to expand the accuracy and range of passive circuit libraries, including parasitic models and entire circuits. |
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| Firms address 65nm FPGA design verification
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2007-09-24 |
| Xilinx has partnered with Cadence, Mentor and Synopsys to define and implement new verification flows for ultrahigh-density designs of 65nm FPGAs and new emerging FPGA architectures |
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| Magma, UMC team release verification, DFM tools for 65nm
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2007-09-24 |
| Magma has partnered with UMC to deliver a broad physical verification and DFM solution for 65nm designs |
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| Xilinx to develop India centre as global R&D hub
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2007-09-19 |
| Xilinx has announced initiatives to develop its India R&D centre, which will play a crucial role in the entire chain of global R&D activities including IP core development, software development and systems and applications. |
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| Rambus, Cadence jointly develop verified PCIe solutions
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2007-09-06 |
| Rambus and Cadence have collaborated to provide designers with an independently verified PCIe solution that seamlessly integrates Rambus' design IP with the Cadence's automated verification IP |
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| Using emulation for system level sign-off
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2007-09-04 |
| Today EDA vendors are hard at work extending the range of tools supporting sign-off to meet the changing landscape introduced with the nanometre age. |
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| Study offers a way to re-suse lead-containing parts
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2007-08-30 |
| A joint study by E-Certa Inc. and Sanmina-SCI was developed to verify the conversion process for leaded components to Pb-free and RoHS-compliant parts. |
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| EDA Tech discusses new technologies
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2007-08-29 |
| EDATF, a key technical and networking resource for the EE community, provided a platform to exchange ideas and preview upcoming technologies in EDA and identify the complete and practical solutions to tackle today's design challenges. |
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| ESC, EDA&T-Taiwan showcased Asia's faster uptake on software, IP
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2007-08-29 |
| The ESC-Taiwan and EDA&T-Taiwan shows seemed a testament to Asia's faster uptake on software and IP industries, given semiconductor industry's evolution and software?s increasing stakes in it. |
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| Software, IP solutions dominate ESC-Taiwan, EDA&T-Taiwan
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2007-08-29 |
| Software and IP solutions took the centerstage at this year's ESC-Taiwan and EDA&T-Taiwan show in Taipei last August 23-24. |
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| Synopsis missing in OVM initiative
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2007-08-23 |
| Despite Synopsis' role in creation of SystemVerilog, Cadence and Mentor made no attempt to invite Synopsis to join and extend the benefits of the OVM initiative worldwide. |
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| Cadence, Mentor team to standardise OVM
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2007-08-22 |
| Cadence and Mentor Graphics have partnered to standardise on OVM that promises to deliver a tool-independent solution for designers and verification engineers that promotes data portability and interoperability |
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Strange modes of transport and other "stuff"
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