| Free IEEE 1685 IP reuse standard gets high traffic
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2010-12-23 |
| The IEEE 1685 standard programme sponsor, Accellera says its standard for IP reuse has been downloaded more than 1,200 times in the past six months since it first became available in June |
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| IP reuse needs a verification strategy
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2005-12-22 |
| The concept of reuse seems simple and easy in theory, but there are a number of obstacles that design and verification teams must address to be successful |
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| IBM pioneers IC wafer reclamation process
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2007-11-05 |
| IBM has pioneered a new IC wafer reclamation process that removes the IP from the wafer surface, making these wafers available either for reuse in internal manufacturing calibration as "monitor wafers" or for sale to the solar cell industry |
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| Altera, Synopsys team to offer Nios II for ASIC designs
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2007-11-15 |
| Utilising its core competencies in design-for-reuse, IP packaging methodologies and design flows, Synopsys will provide a configurable, fully synthesizable version of the Altera Nios II processor core optimised for ASIC implementation |
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| Panelists ponder challenges of 45nm
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2005-11-08 |
| The move to the 45nm process node will be costly and challenging, but worth it for selected applications, according to panelists at the EDA Tech Forum here Thursday (Nov. 3 |
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| OCP-IP launches NoC benchmarking initiative
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2007-03-08 |
| Providing a way to compare performance, cost, and other features of multi-processor SoC architectures, the Open Core Protocol International Partnership (OCP-IP) is launching a network-on-chip (NoC) benchmarking initiative. The first deliverable is a new white paper that outlines the essential features of an NoC benchmarking environment |
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| Synopsys preps for 'techonomic' challenges
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2008-07-01 |
| Synopsys CEO Aart de Geus: I call the challenges "techonomic" because technology and money affect each other. |
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| Challenges ahead for FPGA market
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2008-12-15 |
| The FPGA business faces four major challenges including the fact that the EDA tools are running out of gas. |
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| Mephisto tools IMEC's green radios program
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2010-02-25 |
| In collaboration with Mephisto Design Automation (MDA), IMEC will use MDA's M-Design to develop mixed-signal reconfigurable radios for its green radios program. |
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| Sparring continues at semi IP industry
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2008-09-30 |
| For some time, the semiconductor IP industry has been the virtual and ongoing punching bag in the IC business |
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| FSA signs MoU to establish IP trading centre
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2006-06-23 |
| The FSA has signed a memorandum of understanding with three other groups to establish the Greater China Semiconductor Intellectual Property Trading Centre. |
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| Engineers demo new verification planning process
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2008-06-18 |
| Two engineers recently demonstrated a formal verification planning process at a conference in India. |
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| Global conference series makes a pit stop at India
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2009-11-17 |
| EE Times-India caught up with Rahul Arya, marketing and technical sales director at Cadence Design Systems (I) Pvt. Ltd, to discuss India's domestic semiconductor industry and to find out what Indian engineers should expect at the CDNLive!. |
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| Denali, Spirit Consortium sign IP-XACT development collaboration
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2006-07-31 |
| Denali Software Inc. has said that it would work with the Spirit Consortium on development of IP-XACT to ensure that the consortium data model is aligned with SystemRDL |
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| Accellera pushes for IP tagging standard
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2011-05-02 |
| Accellera pushes for the creation of an IP tagging standard to track soft IP information, particularly from third party vendors to satisfy contractual obligations such as royalty reporting and usage |
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| QIP metric upgrade may ease IP selection
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2006-02-16 |
| Selecting silicon intellectual property (IP) may get a little easier, as the VSI Alliance has released its QIP Metric 2.0 for free |
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| IEEE approves SystemC standard based on SystemC 2.1
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2005-12-14 |
| IEEE has said that it has approved the SystemC electronic design language standard. IEEE standardization may help bring SystemC into more widespread use and pave the way for further support from commercial EDA tools. |
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| Breaking the IC verification barrier
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2006-06-01 |
| Startup OneSpin Solutions believes that it has technology that will usher in an era of IC formal verification. |
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| Growth areas for chip market capitalisation
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2011-01-18 |
| Accenture's Scott Grant presents growth areas that will help semiconductor companies accelerate towards high performance and capitalise on the market upturn. |
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| Broadcom focus on mobile market, ramp shift to 65nm
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2008-03-17 |
| Broadcom is moving in two directions: entering the cellphone market and ramping the shift to 65nm. |
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| IBM, Chartered, Samsung license ARM's 45nm tech
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2006-10-31 |
| Common Platform technology business partners IBM, Chartered Semiconductor Manufacturing and Samsung Electronics Co. Ltd have licensed ARM's proprietary products for 45nm LP process technology. |
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| Saifun Semi adopts Cadence AMS kit
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2006-04-28 |
| Cadence Design Systems Inc. has announced that Saifun Semiconductors has adopted Cadence's Analog Mixed Signal Methodology Kit. |
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| TSMC IP alliance gets a new member
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2010-10-15 |
| MIPS Technologies Inc. expands its relationship with TSMC by joining TSMC's Soft IP Alliance Programme |
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| Accellera merges with The Spirit Consortium
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2009-06-16 |
| The two EDA industry organisations aim to improve the development of language-based and IP standards |
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| Process migration moves in multiple directions
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2009-06-12 |
| Process migration is not only occurring, but it is occurring in all directions: down, up and sideway. |
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| FSA forges alliance with Design and Reuse
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2005-09-09 |
| FSA, the voice of the global fabless business model, has formed an alliance with Design and Reuse (D&R), a company that provides a global collaboration network for sharing design resources in the SoC electronics industry |
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| Wipro joins PFI, offers low-power design
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2008-09-11 |
| Wipro is now a member of Power Forward Initiative, and is offering CPF-enabled low-power design capabilities. |
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| Intel pursues low-power SoC applications
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2011-07-29 |
| Intel's SoC engineering group gears up software, graphics, IP and interconnect assets to create complete SoC solutions aimed at leading performance per watt at 22nm and below |
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| 45nm designs face I/O planning, placement challenges
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2007-11-01 |
| With the move to the 45nm process node, more chip designs are going to be pad-limited, and die sizes will be directly affected by how I/Os are placed and sequenced efficiently.. |
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| Canon India centre taps Mentor OVM platform
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2010-01-13 |
| Mentor Graphics offered extended support for the migration of the Canon India design centre to it's Questa advanced verification platform |
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Strange modes of transport and other "stuff"
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