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PCIe 3.0 compliance testing postponed to 2011 2010-06-25
The PCI SIG released interim ver.0.71 of the 8GT/s PCIe 3.0 bus and plans to start testing for compliance in early 2011, about a year later than originally anticipated  
LSI, Seagate join forces on PCIe storage solutions 2010-02-08
LSI Corp. and Seagate Technology will jointly deliver PCIe based solid-state storage (SSS) solutions for data centre and cloud computing environments  
UWB teams up with PCIe 2007-11-01
The convergence of UWB and PCIe in the notebook will drive high-performance wireless connections for PANs and other short-distance I/O applications. This article examines the trends  
AMD, HP pitch for PCIe 3.0 extensions 2009-08-05
Advanced Micro Devices and Hewlett-Packard researchers have written two extensions to the PCIe 3.0 specification to enable lower cost chips that could support multiple protocols and reduce processor overhead  
Coming soon: PCIe at 8GHz 2009-07-20
PCI Special Interest Group has disclosed that the final specification for PCIe 3.0 will be released by June 2010  
PCIe 2.0 spec doubles transfer rate 2007-01-18
PCI-SIG, the Special Interest Group responsible for the PCIe standard, has released the PCIe base 2.0 specification, which doubles the interconnect bit rate from 2.5GTp to 5GTps to support high-bandwidth applications  
General-purpose PCIe approach ends 2008-06-02
General-purpose switching and bridging components no longer have a place in demanding PCIe-based systems  
PCIe spec extends 'outside the box 2007-02-13
PCI-SIG has released the PCIe external cabling 1.0 specification, which extends the PCIe interconnect architecture 'outside the box  
PLDA, EVE partner on PCIe verification 2006-03-06
PLDA and EVE have forged a partnership on PCIe verification. With the integration of PLDA's PCI-SIG-compliant x4 PCIe Xpress IP, EVE's ZeBu now supports rapid verification of PCIe-based SoC designs  
Industry analyse PCIe 3.0 draft spec 2007-08-14
The details of the draft spec for PCIe 3.0 have triggered a debate in the industry  
PCI-SIG announces PCIe Spec 3.0 2010-11-25
The PCIe Base 3.0 spec announced by the PCI-SIG doubles the interconnect bandwidth over the PCIe 2.0 spec to achieve bandwidth near 1GByte/s in one direction on a single-lane configuration  
Rambus, Cadence jointly develop verified PCIe solutions 2007-09-06
Rambus and Cadence have collaborated to provide designers with an independently verified PCIe solution that seamlessly integrates Rambus' design IP with the Cadence's automated verification IP  
PCI-SIG enhances PCIe ver 2.0 2007-01-16
The PCI-SIG is making progress on feature extensions to its latest 2.0 spec that could enhance system performance as well as smooth a path for accelerators and storage devices riding the interconnect.  
PCI group sets 8GT/s bit rate for PCIe 3.0 2007-08-10
The PCI Special Interest Group has finally set 8GT/s as the bit rate for the PCIe 3.0 version  
Server chipmakers prepare 10GbE for PCIe, virtualisation 2008-02-15
Server makers are hoping to be able to deliver a variety of networking, storage and clustering features on Ethernet for systems that can host multiple sessions at once, thanks to virtualisation tech.  
Flash drives push Serial ATA, PCIe merger 2011-08-12
The SATA International Organisation is working on a new SATA Express standard that will use PCI Express to support data rates of 8 and 16Gb/s to cater to the enhanced needs of solid-state and hybrid drives.  
PCI-SIG targets PCIe Gen 4 with 16GTps throughput 2011-06-28
The PCI Special Interest Group is working on getting at least one more high-speed, 16GTransfers/s version of PCI Express from copper links before the anticipated shift to optical interconnects.  
PCIe goes everywhere 2008-07-22
PCI Express has become the leading chip interconnect, dominating in servers, storage systems and PCs.  
PLX defines plan for Ethernet tunnelling in PCIe 2008-11-26
PLX Technology Inc. has defined a way to run Ethernet over its PCI Express switches.  
PCIe shifts gear into v2.0 2006-06-13
The 2.5Gbps PCI Express interconnect is slowly shifting gears into a 2.0 version.  
PLDA, Rapid Bridge join hands to produce ASIC solution 2006-07-27
PLDApplications (PLDA) and Rapid Bridge Systems have announced an agreement to pool their PCIe proficiency to produce an ASIC solution  
SSD Form Factor Working Group pushes for standardisation 2010-11-02
The Solid State Drive Form Factor Working Group formed of several companies are advocating the development of PCIe storage drives through standardisation  
Fujitsu adopts ARM Velocity's standard cells 2006-12-13
ARM's Velocity PHY for PCIe Gen-2 and the Advantage v2.0 standard cell library has been adopted by Fujitsu Ltd on its CS200 HP 65nm platform. The agreement enables Fujitsu to offer foundry customers access to ARM physical IP, which provides an optimal design solution for advanced LSI development  
Micron acquires storage virtualizer, Virtensys 2012-01-24
Micron Technology's purchase of Virtensys is seen to strengthen Micron's enterprise storage portfolio by letting it pair its solid state drives with Virtensys' PCIe virtualisation technology  
Cadence, IBM team on high performance IPs 2010-05-28
Cadence Design Systems, Inc. and IBM have signed an agreement to develop DDR PHYs, memory controllers, and protocols such as PCIe and Ethernet under 32-nanometer silicon-on-insulator  
PCI Express aims to match Thunderbolt 2011-06-24
PCSIG launches an effort to develop a cabled interconnect that will be based on PCIe 3.0 for delivering high throughput I/O to tablets and thin notebooks  
Broadcom bares 3G RAID architecture at IDF 2005-08-24
Broadcom Corp. is demonstrating what it claims to be the first SAS/SATA RAID-on-Chip (RoC) device with integrated PCI Express (PCIe) host bus architecture support at the ongoing Intel Development Forum 2005 (IDF) in San Francisco  
HyperTransport group upgrades HTX spec 2008-08-20
The HyperTransport Consortium is giving a boost both to its chip-to-chip interconnect as well as a board-to-board version.  
High-speed interconnects carry data at 6Gbps 2007-02-02
A handful of high-speed interconnects are driving changes in how designers handle fast signals. The SPI-S from the OIF aims to carry data at 6Gbps and up between chips or boards in a communications system.  
Midsize motherboards diversify 2008-06-02
Midsize motherboards diversify, ranging from about 40-50-inch2, the activity centers primarily on 6.7-inch x 6.7-inch Mini-ITX and 5.75-inch x 8-inch EBX motherboards.  


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