| Chip makers, EDA vendors set up DFM coalition
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2007-09-21 |
| The Silicon Integration Initiative (Si2) has announced that top chip makers and EDA tool vendors have established a coalition to add DFM parameters to existing design flow. |
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| Sierra Design offers alternative to traditional P&R solutions
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2006-08-09 |
| Sierra Design Automation has recently that announced Olympus-SoC is positioned to offer physical IC designers an alternative to traditional P&R solutions. |
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| TSMC to exit Sematech, may join IMEC
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2005-08-03 |
| Taiwan Semiconductor Mfg Co. will give up its membership in International Sematech later this month, and is |
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| Albany NanoTech primes 300-mm R&D fab
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2008-09-23 |
| Albany NanoTech's massive new facility will focus on 22-nm R&D technology, post-CMOS processes and clean technology. |
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| Breakthrough in Si-based all-optical ICs reported
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2009-04-17 |
| Transmission speeds beyond 100Gbps based on silicon devices have become possible through an American-European research team. |
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| LCD business seeks new drivers amid downturn
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2008-12-15 |
| LCD makers at Samsung are seeing solar as one of the most promising drivers of future demand. |
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| 3D buzz centres on TSVs
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2008-06-09 |
| Through-silicon vias technology continues to generate steam. |
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| IBM rolls 'computational scaling' for 22-nm node
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2008-09-19 |
| IBM Corp. plans to move towards what it calls ''computational scaling'' technology for the 22-nm node. |
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| Semicon-equipment market to continue consolidation
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2006-07-20 |
| For years, the semiconductor-equipment market has seen its share of consolidation. Expect this trend to continue in 2006 and beyond, according to one semiconductor-equipment veteran. |
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| Circuit designers take control over layout parameters
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2007-02-16 |
| To help schematic simulation closely match post-layout simulation, the designer must predict how schematic devices will be combined in the layout and gain control over the parameters used to model the layout characteristics. |
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| Speculations cast on semiconductor technology roadmaps
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2010-12-15 |
| With fewer papers this year at the IEDM, and chipmakers reluctant to divulge plans for 22-/20nm, rumours abounded that leading-edge foundries will extend bulk CMOS. |
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| Fujitsu's new 300mm fab starts operation
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2007-04-12 |
| Fujitsu Ltd. has begun operating its second 300mm wafer fab for 65nm chip fabrication. Volume shipments will begin in July. |
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| IBM pitches air gaps as 'ultimate' dielectric
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2007-06-18 |
| IBM Corp. has vowed to commercialise the ultimate dielectric?a pure vacuum?between metal lines of its 32nm chips, thereby reducing parasitic capacitance on interconnection layers by 36 per cent. |
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| Chartered plans to develop 28-nm process
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2008-09-26 |
| Chartered said it is planning to develop and offer a 28-nm process possibly by next year. |
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| Printed electronics: Next step beyond silicon ICs
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2007-11-22 |
| Many organisations are seeking shares of a TFT and memory market that IDTechEx predicts will grow from nearly zero to Rs.158.20 crore ($40 million) by 2009 and Rs.31,639.87 crore ($8 billion) by 2017. |
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| Toppan, IBM to develop 32nm photomask process
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2008-06-23 |
| Toppan has entered into an agreement with IBM that covers the last phase of 32nm photomask process development. |
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| Despite downturn, TSMC invests in R&D
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2009-04-23 |
| TSMC remains cautiously optimistic about the IC industry and vowed that it will continue to invest in R&D despite the downturn. |
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| Industry challenges in IC scaling
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2010-12-13 |
| The cost and expense of chip scaling as IC technology enters sub-20nm era could drive the industry to migrate to 3-D devices, based on through-silicon via (TSV) technology, says technologist from Samsung. |
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| Engineers demonstrate smallest silicon modulator
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2006-02-17 |
| Electrical engineers at the University of Texas in Austin have demonstrated what they claim is the smallest silicon modulator. The device features a photonic-crystal waveguide with an electrode configuration that they hope will make it easy to manufacture. Such a compact modulator might be the key to building practical all-silicon lasers, they said. |
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| Nvidia joins Imec's Insite CMOS scaling programme
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2011-05-30 |
| Nvidia has entered a three-year collaboration agreement with Imec for its Insite CMOS scaling programme, which focuses on the system design impact at sub-20nm nodes. |
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| 3D-TSVs usher in packaging revolution
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2008-09-01 |
| 3D-TSV wafers could account for more than 6 per cent of the total semiconductor industry by 2015. |
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| IMFT NAND flash fab commences by Q2 2011
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2010-12-22 |
| IM Flash Technologies LLC is preparing to commence commercial production in its delayed wafer fab in Singapore by the second quarter of 2011. |
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| Intel-Micron duo rolls 34nm NAND device
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2008-06-02 |
| IM Flash Technologies LLC developed the industry's 'first' sub-40nm NAND flash device. |
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| Intel gears for 32nm chip launch
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2009-09-16 |
| The Intel Corp. Senior Fellow Mark Bohr presented highlights of the company's latest process technology at the company's latest briefing. |
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| IMEC, Qualcomm broaden 3D research agreement
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2011-05-27 |
| IMEC and Qualcomm have broadened their partnership on 3D process technology research to participation in IMEC's INSITE programme. |
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| Intel to extend lead in high-k
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2008-12-12 |
| Intel is expected to extend its lead over other microprocessor vendors in the high-k/metal-gate race. |
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| Renesas moves to fab-lite model gradually
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2007-10-25 |
| Renesas Technology is seeking to make up ground at the 65nm node and beyond by quietly altering its fab and foundry strategies. |
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| MagnaChip ups capex, tips 130nm process
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2005-10-14 |
| Amid a plan to boost its capital spending, South Korea's MagnaChip Semiconductor Ltd is developing a new 130nm process technology for a range of applications. |
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| Industry players discuss standard for Open DFM
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2006-10-04 |
| Participants of the Open DFM Model Workshop have explored issues ranging from DFM flows to encryption and identified possible next steps. |
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| Cadence acquires Invarium, addresses 45nm challenges
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2007-07-17 |
| Cadence has acquired Invarium to enhance its ability to address the 45nm and below patterning challenges that include double patterning, printability and scaling of very fine features. |
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Strange modes of transport and other "stuff"
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