| Calypto hosts seminar on ESL methods for RTL design
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2006-12-20 |
| Calypto Design Systems (India) Pvt. Ltd hosted a half-day seminar titled 'ESL methods for RTL design and verification' in November 2006, with its distributor CMR Design Automation |
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| Dongbu, Cadence develop reference flow for RTL to GDSII
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2006-05-26 |
| South Korean fab Dongbu Electronics has teamed up with Cadence Design Systems to jointly develop the DBE 130.2, an RTL-to-GDSII reference flow |
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| Atrenta releases RTL design textbook
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2011-06-03 |
| Atrenta Inc. releases a comprehensive textbook on RTL design entitled "Principles of VLSI RTL Design, A Practical Guide", authored by Sanjay Churiwala and Sapan Garg |
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| Synopsys offers RTL-to-GDSII ref design for 90nm process
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2006-03-07 |
| Synopsys Inc. has announced that it has delivered an enhanced version of its RTL-to-GDSII low-power reference design flow for the latest 90nm process |
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| VERTIGO to check on TLM, RTL standards
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2007-02-08 |
| The Commission of the European Communities within the I ST area has launched a project to bridge the gap between system-level modelling and verification performed at the transactional level and the traditional RTL signoff description |
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| Synopsys offers RTL-to-GDSII design system
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2006-04-18 |
| Synopsys Inc. is offering its customers the Pilot Design Environment, an integrated RTL-to-GDSII design system tailored to each customer's design infrastructure |
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| SMIC, Magma offering RTL-to-GDSII flow for 130nm SoCs
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2005-11-21 |
| Magma Design Automation Inc. and Semiconductor Manufacturing International Corporation (SMIC) have made available a validated reference flow based on Magma's Blast Create, Blast Plan Pro, Blast Fusion and Blast Power for system-on-chips (SoCs) targeted at SMIC's 130nm process. |
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| Tool gets a handle on voltage changes
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2005-08-16 |
| As a chip designer for Intel Corp., Srikanth Jadcherla spent a lot of time working on multivoltage designs. Now he's launched an EDA startup, ArchPro Design Automation Inc., which is rolling out what it presents as the industry's first multivoltage RTL simulation product |
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| Cadence, IBM team up to accelerate ASIC design
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2006-11-15 |
| Cadence Design Systems Inc. has signed an agreement with IBM to incorporate Encounter RTL Compiler global synthesis and Cadence Encounter Test technologies into IBM's 65nm ASIC design kit |
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| Global UniChip improves silicon quality with Cadence tech
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2005-08-02 |
| Cadence Design Systems Inc. disclosed that Taiwan-based Global UniChip Corp. has adopted Cadence Encounter RTL compiler global synthesis, part of the Encounter digital IC design platform, to improve the quality of silicon (QoS) of its hardened IP |
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| TSMC qualifies Magma Quartz tech for nanometre designs
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2007-06-27 |
| With Quartz RC and the Magma Blast and Talus RTL-to-GDSII systems qualified by TSMC, designers can address new variables prevalent in 65nm, 90nm and 130nm designs to deliver the required level of accuracy |
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| Cadence solution enables Taiwan's first 65nm IC design
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2007-03-15 |
| Cadence Design announced that Global Unichip was the first Taiwan-based design company to complete a successful tape-out of a 65nm device with the use of Cadence Low-Power Solution and SoC Encounter GXL RTL-to-GDSII system |
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| GN ReSound chooses Magma Design's Talus system
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2010-10-08 |
| Hearing instrument maker selects Talus RTL design solution for high-performance next-gen ICs for optimal power/performance trade-off |
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| Melfas taps Magma's Talus for touch sensor chips
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2010-12-07 |
| Melfas taps Magma's Talus RTL, Vortex, and Power Pro tools and FineSim SPICE circuit simulation tool to implement two MCS-8000 touch sensor chips |
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| Synopsys, SMIC jointly develop ref design flow 3.0
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2006-09-07 |
| Synopsys Inc. and SMIC have jointly developed and deployed reference design flow 3.0. |
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| DongbuAnam, Synopsys develop 130-nm reference flow
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2005-11-07 |
| Korean wafer foundry DongbuAnam Semiconductor Inc. and EDA giant Synopsys Inc. have jointly developed a reference flow for DongbuAnam's 130nm process, the companies said Friday (Nov. 4). |
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| FPGA start-up Achronix defying gravity
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2009-04-27 |
| FPGA start-up Achronix has the technology and financial stability to weather the current downturn, according to its CEO. |
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| Open-Silicon joins TSMC's design center alliance
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2005-08-26 |
| Fabless ASIC supplier Open-Silicon Inc. has joined Taiwan Semiconductor Mfg Co. Ltd (TSMC)'s design center alliance program. |
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| Re-synthesis solution offers area, speed, power benefits
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2007-05-28 |
| Nangate Inc. has claimed that its Design optimiser solution is capable of creating an optimised gate-level design with area, speed or power benefits. |
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| Using emulation for system level sign-off
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2007-09-04 |
| Today EDA vendors are hard at work extending the range of tools supporting sign-off to meet the changing landscape introduced with the nanometre age. |
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| NVIDIA licenses NextOp's BugScope
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2011-05-05 |
| Graphics company NVIDIA signs a multi-licence agreement with NextOp Software Inc. for expanded use of NextOp's BugScope assertion synthesis product. |
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| Atrenta, TSMC join forces on synthesisable IP
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2010-10-28 |
| Atrenta Inc. and Taiwan Semiconductor Manufacturing Co. Ltd are cooperating to improve the quality of delivered synthesisable IP using Atrenta's SpyGlass platform. |
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| Die, package design get closer
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2005-11-01 |
| Targeting designs headed for flip-chip packages, Synopsys' floor-planning and analysis tool enables concurrent die and package design flows. |
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| Engineers write up SystemC TLM concepts
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2005-09-01 |
| Engineers at STMicroelectronics claim that SystemC transaction-level modeling will be the next SoC design methodology. |
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| Vendors support SystemVerilog synthesis
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2006-04-19 |
| Synthesis vendors are strongly supportive of a proposed standard SystemVerilog synthesis subset. |
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| Challenges ahead for FPGA market
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2008-12-15 |
| The FPGA business faces four major challenges including the fact that the EDA tools are running out of gas. |
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| Denali spreads new word in ESL mart
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2005-10-03 |
| With a missionary zeal to establish standards and design methodologies, Denali Software leaps into the ESL market. |
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| Success story of an APAC EDA player
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2008-01-02 |
| The hardware capabilities of Taiwan's high-tech industry are well known. However, the industry is relatively weak in its software capability. Meanwhile, in the semiconductor sector, the three biggest EDA suppliers hold about 90% of the market. |
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| Verification moves up a level
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2005-12-19 |
| With the introduction of languages and transaction-level modelling, designers can think and work at higher levels of abstraction. |
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| EnSilica, Evatronix tie on eSi-RISC connectivity
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2011-06-02 |
| EnSilica and Evatronix SA collaborate on the development of the eSi-RISC processor SoC equipped with USB 1.1, 2.0 and 3.0 connectivity. |
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