| Synplicity unveils ASIC/ASSP verification solution
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2007-06-13 |
| Synplicity's Confirma platform is a tightly integrated, hardware-assisted ASIC/ASSP verification solution that brings together hardware and software tools |
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| ARM to sample verification IP for on-chip comms
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2007-06-12 |
| ARM plc will start sampling its lead partners AMBA Adaptive Verification IP for on-chip communication during the third quarter |
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| iC-HQ op amp suits high gain sensor apps
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2007-06-04 |
| iC-Haus GmbH's new unity gain stable quad op amp suits signal conditioning and amplification, particularly in sensor applications with extremely high gain. |
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| Car information SoC delivers 1GIPs performance
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2007-06-01 |
| Renesas SuperH family SH7775 of SoC is capable of high processing performance of 1GIPS or more for car information systems such as car navigation systems. |
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| Quartus II upgrade vows 2x faster compile times
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2007-05-31 |
| Altera's Quartus II software version 7.1 enables customers to begin designing for the entire Arria GX FPGA family in both the subscription edition and web edition of Quartus II software. |
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| Verification solution aids FPGA-based ASIC prototyping
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2007-05-31 |
| Synplicity's Identify Pro verification tool provides full visibility into FPGA-based ASIC/ASSP prototypes enabling you to find and fix functional errors at speeds approaching that of the final device |
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| SoftJin launches layout and mask data comparison tool
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2007-05-25 |
| SoftJin's NXCompare compares any two layout and/or mask databases, which may be in different formats, have different hierarchies or come from different sources. |
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| ArchPro launches multi-voltage verification tool
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2007-05-24 |
| ArchPro's MaVeric software verifies a multi-voltage design through an architecture-based, multi-voltage profiling and "Electrically Accurate" verification |
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| Cadence simulators claim zero correlation error
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2007-05-18 |
| Cadence announced the release of 6.2 version of its Virtuoso MMSIM tool that allows designers to switch from one simulation engine to another without compatibility issues or interpretation problems. |
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| Kit provides access to low-power design techniques
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2007-05-17 |
| Cadence low-power methodology kit increases accessibility of low-power IC design techniques. |
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| Test software publishes results to secure website
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2007-05-15 |
| VI Technology's Arendar 2007 version provide instant access to design, characterisation, validation and verification, and manufacturing test information across the enterprise |
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| Tool generates VisualDSP++ projects from Simulink models
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2007-05-10 |
| A new tool from MathWorks and Analog Devices generates VisualDSP++ projects from Simulink models. |
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| Mentor-Anite platform targets handheld devices
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2007-05-03 |
| Anite is partnering with EDA group Mentor Graphics on a complete verification platform that will provide an integrated and efficient set up to verify base band SoC designs |
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| GateRocket rolls device-native verification for FPGAs
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2007-04-25 |
| Start-up GateRocket is offering a device-native FPGA verification tool that includes hardware and software |
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| Synopsys Design Compiler boosts IC performance
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2007-04-24 |
| Synopsys' Design Compiler 2007 synthesis solution extends topographical technology for designs utilising advanced low-power and test techniques. |
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| Tool delivers enhanced floating-to-fixed-point conversion capabilities
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2007-04-23 |
| The MathWorks has announced Fixed-Point Tool-Box 2, which provides enhanced floating-to-fixed-point conversion capabilities and accelerated fixed-point MATLAB algorithms that execute at compiled C-code speed. |
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| DSPs provide high DSP performance at low cost points
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2007-04-20 |
| Targeting to establish a new price-performance-power triad for DSP, Xilinx Inc. unveiled its low-cost Spartan-DSP series with development boards and enhanced design software. |
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| Tool eases addition of digital filter in audio apps
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2007-04-10 |
| Quickfilter Technologies announced a new product designed to simplify the addition of precision digital filtering to audio applications. |
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| Optical receiver stress tester provides repeatable test results
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2007-04-04 |
| Agilent Technologies introduced a complete optical receiver stress test solution—the N4917A—which provides repeatable conformance and characterisation test results. |
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| Synopsys rolls design platform supporting UPF 1.0
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2007-04-02 |
| Synopsys Inc. has announced a low-power design flow that will implement the Accellera Unified Power Format version 1.0 in its IC verification and implementation products in the second half of 2007 |
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| Tool automatically adds clock-gating logic to RTL code
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2007-03-28 |
| Claiming breakthrough technology in IC power optimisation, Calypto Design Systems is announcing PowerPro CG, a tool that automatically adds clock-gating logic to RTL code. |
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| Aldec unveils co-verification solution for Actel FPGAs
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2007-03-14 |
| Aldec has announced the release of CoVer, a Windows-based HW/SW co-verification solution for Actel's ARM-based FPGAs |
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| Magma Design claims first parallel fast Spice
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2007-03-12 |
| Magma Design announced the availability of the FineSim Pro Parallel Manager, claimed to be the first parallel fast Spice capability targeting the verification of large mixed-signal SoCs. Targeting the verification of large mixed-signal SoCs, FineSim Pro Parallel Manager can run the simulator over distributed networks, or multiple-CPU workstations |
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| FC CPU chip easily interfaces with FPGA devices
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2007-03-05 |
| Faraday Technology Corp. has announced the FPGACompanion CPU chip, targeted at system companies who need a full-featured ARM CPU chip that can easily be interfaced to various FPGA devices. |
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| C++ verification class library rolls
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2007-02-23 |
| Jeda Technologies is introducing NSCv, a C++ verification class library for SystemC. The offering supplements the open-source SystemC Verification Library (SCV) with functional data coverage, dynamic threading and memory management capabilities |
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| Embedded tool cuts project expenditure time
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2007-02-23 |
| IAR Systems has launched the visualSTATE 5.4, the latest version of its state machine embedded design and verification tool with a tighter integration to IAR Embedded Workbench |
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| Statistical tool avoids overdesign
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2007-02-14 |
| Solido Design Automation has taken the wraps off technology that will provide transistor-level statistical design and verification. The company promises to take Monte Carlo analysis "to the next level" with additional capabilities |
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| Elektrobit intros latest version of air interface emulator
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2007-02-13 |
| Elektrobit is introducing a version of the air interface emulator Propsim FE with more compelling functionality. |
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| Actel develops controller cores optimised for FPGAs
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2007-02-07 |
| Actel Corp. has introduced two free controller cores; the small, easy-to-use CoreABC and the configurable Core8051s. These cores complement the company's existing library of industry-standard options. |
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| Cadence develops 'first' complete low-power solution
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2007-02-02 |
| Cadence Design Systems has announced that it has developed a low-power solution, the industry's first fully integrated flow for logic design, verification and implementation of low-power chips |
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Strange modes of transport and other "stuff"
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