| HDL tool suite cuts cycle times, respins
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2005-10-11 |
| Mentor Graphics announced the release of a new concurrent design checking and creation environment, available in the latest version of the HDL Designer Series tool suite |
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| Mentor, MathWorks collaborate on optimised FPGA design flow
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2007-11-23 |
| Mentor Graphics and MathWorks have collaborated on HDL generated by MathWorks Simulink HDL Coder in Mentor?s Precision suite of advanced synthesis products to provide a rapid path from Simulink models to FPGA implementation |
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| Aldec unveils Riviera-PRO 2008.10
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2008-11-19 |
| The Riviera-PRO 2008.10 is an HDL mixed-language simulator for multi-million gate ASIC and FPGA designs |
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| Actel unveils block-based FPGA design
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2007-06-20 |
| Actel Corp. is unveiling SmartDesign, a graphical design entry capability that lets users graphically create block diagrams from prefabricated blocks from Actel's DirectCore and SmartGen IP libraries, and supports custom blocks written in HDL code |
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| Aldec introduces multi-threaded VHDL compilation
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2007-12-24 |
| Aldec has announced the release of Active-HDL 7.3 that includes multi-threaded HDL compilation, new waveform viewer and expanded VHDL 2006 construct support |
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| Upgraded tool suite enhances CPLD design
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2010-08-23 |
| Lattice Semiconductor Corp. unveils version 1.4 of its ispLEVER Classic design tool suite to include Synopsys Synplify Pro with the HDL Analyst feature set, and an ispMACH 4000ZE CPLD fitter |
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| FPGA development tool upgraded with new simulation capability
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2005-11-18 |
| Version 5.1 of the DSP Builder development tool from Altera is designed to enable FPGA designers to simulate an imported HDL design within The MathWorks Simulink environment |
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| Aldec rolls out ALINT 2008.10
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2008-12-11 |
| Aldec Inc. says ALINT reduces risk when developing complex multi-million gate ASICs. |
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| MataiTech rolls out ESL tool to prevent bug at source
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2006-08-18 |
| MataiTech LLC has rolled out Nauet, an ESL tool that lets hardware and software engineers collaborate at the earliest stages of a design, thus preventing bugs at the source. |
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| DSP builder improves designers' productivity
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2008-07-02 |
| Altera rolled its DSP Builder tool version 8.0, featuring second-generation model-based synthesis technology. |
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| Software tools extend support for nano FPGAs
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2008-12-11 |
| Libero IDE 8.5 also offers high-speed multiplier instantiation for RTAX-DSP applications. |
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| Lattice PCIe IP meets PCIe v2.0 requirements
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2011-07-08 |
| Lattice says its LatticeECP3 FPGA and PCI Express (PCIe) IP core are now PCIe v2.0 compliant enabling cost and power savings for communications, multimedia, server and mobile platforms. |
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| Synopsys testbench solution increases verification productivity
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2005-09-30 |
| Synopsys announced Discovery Pioneer-NTB, a new SystemVerilog testbench automation tool that claims to increase verification productivity and improve the quality of complex SoC and IP designs. |
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| Web IP configuration tool for IC designers debuts
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2007-10-23 |
| Think Silicon has developed an online IP configuration platform for the generation of parametrisable IP modules than can be used in semiconductor devices.. |
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| Multiprocessor tool suite gets upgrade
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2009-06-22 |
| Multiprocessor design firm 3L has introduced version 3.2 of its Diamond multi-processor tool suite. |
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| FPGA tool aids Simulink development cycle
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2011-06-28 |
| MathWorks launches the xPC Target 5.0, which provides support for FPGAs, extending the rapid prototyping workflow for Model-Based Design. |
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| Soft processor gets free software tools
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2010-10-14 |
| Lattice offers free software tools for LatticeMico8 soft processor, including C-compiler |
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| Design suite enhances FPGA partial reconfiguration
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2010-08-13 |
| Xilinx Inc. releases the ISE Design Suite 12.2, an easier-to-use, intuitive, fourth generation of partial reconfiguration design flow offering an improvement to its intelligent clock gating technology. |
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| Standard improves AMS design
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2008-08-26 |
| Accellera announced that its Board of Directors and Technical Committee members approved Verilog-AMS 2.3. |
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| Dev't board prototypes designs in a snap
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2009-09-23 |
| Altium rolls a new FPGA-based development board that eases instant prototyping of electronic designs. |
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| XMC/PMC module targets real-time apps
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2008-10-14 |
| VMETRO has introduced a new generation user programmable FPGA XMC/PMC module with fibre-optic transceivers. |
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| MATLAB, Simulink revision features code generation
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2011-04-19 |
| MathWorks reveals Release 2011a (R2011a) of its MATLAB and Simulink product families offering key code generation products, MATLAB Coder, Simulink Coder, and Embedded Coder. |
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| Serdes-capable FPGAs tout low power consumption
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2009-02-26 |
| The LatticeECP3 line is aimed to pre-empt new, mid-range introductions from Altera and Xilinx. |
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| 64bit simulator runs 10x faster without FPGA tools
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2010-01-22 |
| From SynaptiCAD comes the first 64bit Linux version of VeriLogger Extreme, a Verilog simulation and debug environment which is 30 per cent faster than the 32bit version. |
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| Xilinx releases ISE WebPACK 8.2i design suite
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2006-07-27 |
| Xilinx Inc. released the ISE WebPACK 8.2i—the latest version of the company's free downloadable programmable logic design suite. |
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| Mathworks' RF Toolbox includes signal integrity capability
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2006-12-15 |
| The Mathworks is rolling out the RF Toolbox 2, which adds time-domain capabilities to this Matlab add-on package. As a result, the company said, engineers can significantly reduce the time needed to develop I/O circuitry for high-speed digital systems. |
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| MathWorks enhances product toolset, features
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2010-09-08 |
| MathWorks presents Release 2010b of its MATLAB and Simulink product families with an expanded toolset and features. |
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| SpringSoft adds verification tech to functional qualification
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2011-05-16 |
| Springsoft has integrated an advanced technology platform to its Certitude Functional Qualification System that enables broader deployment of verification qualification methodologies. |
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| Xilinx adds embedded, DSP, RT debug design flows to tool
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2006-01-16 |
| Xilinx Inc. has announced that the availability of the ISE WebPACK 8.1i programmable logic design tool, which includes all the features of ISE Foundation with full support for embedded, DSP and real-time debug design flows. |
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| Platform delivers faster verification
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2009-04-13 |
| Synopsys Inc. has unveiled the latest generation of its Discovery Verification Platform. |
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