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EE Times India - total search 34 articles sort by date sort by relevance
Mentor's Platform Express supports IP-XACT 1.4 2008-03-25
Mentor has made available a new version of Platform Express that offers a universal method to describe IP for Design Reuse, and enables that IP to be automatically integrated into designs using a range of IP-XACT enabled tools  
Tools bridge chip design, verification with shared database 2010-06-04
Jasper's upgraded ActiveDesign and JasperGold tools bridge chip design and verification by sharing a common, persistent knowledge base.  
FPGA dev't kit supports AXI4 interface protocol 2011-08-23
X-ES announces the availability of the XPedite2300, a Xilinx Virtex-6 based XMC module and the first embedded FPGA development environment based on the AXI4 interface protocol, the XPedite2300 FDK.  
Mentor announces Platform Express product 2006-05-09
Mentor Graphics Corp. has announced that the Platform Express product is the first platform-design solution to support The Spirit Consortium's 1.2 XML specification.  
Altera enhances Quartus II software 2008-11-05
Altera has unveiled Quartus II software version 8.1 for CPLD, FPGA, and HardCopy ASIC designs.  
Forte upgrades Cynthesizer 2005-09-26
Forte Design Systems announced that it has upgraded its Cynthesizer behavioral synthesis solution to provide a more extensive production ESL design flow.  
Freescale develops QUICC III Engine Tech processor family 2006-10-17
Freescale Semiconductor Inc. has announced its PowerQUICC III processor family that offers a Gigahertz CPU core, flexible QUICC Engine technology and high-speed system interfaces for multi-protocol inter-working.  
ARM starts sampling Cortex-R4F processor 2006-10-13
ARM Ltd has started sampling the latest version of its Cortex-R4 processor that is targeted at reducing the cost and design-time of automotive applications. This processor floating point support for faster processing of 32bit designs.  
IP cores aim SoC, ASIC, FPGA designs 2009-03-12
CebaTech has unveiled a library of tunable silicon IP cores targeted at SoC, ASIC and FPGA designs  
Formal verification tool provides fine control over thoroughness 2006-07-27
Averant Inc. has released the next generation of its formal verification tool, Solidify 4.0.  
Cadence unveils UCVs-line of reusable verification IP 2006-08-14
Cadence Design Systems Inc. has introduced the UCVs, a new line of reusable VIP that integrates compliance management and mixed-language flexibility with advanced simulation-based testbench technology.  
OVM extends sequential stimulus mechanism 2008-09-15
Mentor and Cadence has launched the latest version of Open Verification Methodology.  
TI announces digital video software dev kit 2006-06-23
Texas Instruments has announced a digital video software development kit which provides designers greater access to its DaVinci video technology.  
Digital media processors offer 3x HD performance 2011-03-08
TI unveils the TMS320DM8168 and TMS320DM8148 DaVinci digital media processors that offer advanced analytics capabilities for video streaming on up to three independent displays.  
Open-source SystemVerilog solution rolls for OVM 2008-12-08
Mentor has introduced an open-source SystemVerilog solution for users adopting the OVM.  
Design software simplifies hardware integration 2011-08-04
NI launches NI LabVIEW 2011 offering increased development efficiency through engineering-specific libraries and its ability to interact with almost any hardware device.  
Leon 3 Sparc processor supports Linux SMP 2007-03-06
The Leon 3 licensible Sparc processor, developed by Gaisler Research, has symmetric multi-processing support, in the form of a port of the Linux 2.6 OS.  
Xilinx 28nm FPGAs pack two million logic cells 2010-06-23
Xilinx has announced its 28nm series 7 FPGAS that will offer 50 per cent power reduction compared to the company's 40nm devices and up capacity to two million logic cells.  
Reusable IP to accelerate ESL synthesis 2007-02-08
Bluespec Inc. has announced that it will roll out the AzureIP Foundation Library, a set of parameterised IP blocks for use with the company's Bluespec Compiler  
Cadence unveils 'first' transaction-based system verification 2006-06-21
Cadence Design Systems Inc. has unveiled its 'first' automated end-to-end transaction-based system verification and management solution.  
EEPROM block offers up to 180?C temp 2007-05-28
Austriamicrosystems has announced the availability of fully automotive-qualified 3Kb EEPROM blocks that uses PMOS-based NVM technology to offer an industrial temperature range up to 180?C.  
Freescale designs low-cost processor for SOHO apps 2006-11-20
Freescale Semiconductor Inc. has launched its low-cost processor for digital media servers deployed in small-office/home-office (SOHO), IP services and industrial control applications  
Platform enables multicore optimisation tech 2011-02-10
Synopsys' Platform Architect with Multicore Optimisation Technology enables architecture definition, hardware-software partitioning and performance analysis at the concept phase of the design process.  
Custom-defined SoC delivers 350K gates/mm² 2009-08-18
Atmel Corp. is offering a custom architecture for 90nm SiliconCity ASIC development, providing up to 350,000 gates/mm², giving customers gate densities in the range of a standard cell ASIC.  
STARC design flow incorporates Cadence tech 2008-01-24
Cadence has announced that Japan's STARC ultralow power PRIDE reference flow V1.5 has incorporated the CPF-based Cadence Low-Power Solution.  
Motorola RAN solution adds LTE to WiMAX networks 2010-06-23
Motorola's enhanced WiMAX offering is based on a single RAN solution provides operators with a cost-effective way to upgrade their network offerings, preserving capital and protecting investment  
Design data management tool allows scalability, collaboration 2007-04-24
The Global Design Platform from IC Manage is claimed to be the first data-management solution to offer design assembly, derivative management and real-time worldwide delivery.  
Acceleration co-processor eases code compilation 2010-05-11
Plurality Ltd debuts the HyperCore family that represents a new category of acceleration co-processors based on an innovative architecture that simplifies code compilation.  
Compiler optimised to speed up code execution 2010-08-09
National Instruments offers off-the-shelf compiler technologies that have been optimised to execute code an average of 20 per cent faster in LabVIEW 2010.  
TCP/IP stack offers BSD socket interface 2007-06-04
eSOL has announced the release of its PrCONNECT/Pro TCP/IP protocol stack that delivers a data transmission speed of more than 74Mbps and has a rich set of security, routing and other protocols  


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Clive Maxfield Strange modes of transport and other "stuff"

Someone just pointed me at a YouTube video that claims to show the world's first e-powered multicopter flight...

 

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