| Cadence RTL synthesis tool targets chip-level interconnect
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2007-07-11 |
| The new component of Cadence Logic Design Team Solution integrates the Encounter RTL Compiler synthesis tool with the First Encounter floorplanning tool so that synthesis can get timing estimates from physical floorplanning data |
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| Cadence launches Encounter RTL Compiler GXL
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2005-12-08 |
| Cadence Design Systems Inc. has announced an upgraded version of its Encounter RTL Compiler global synthesis technology |
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| Sequence intros first RTL power analysis solution
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2006-07-20 |
| Sequence Design has introduced the first RTL power analysis and management solution with physical-design features to insure results that closely relate to real silicon |
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| Software speeds up RTL power reduction
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2008-05-20 |
| Sequence has released what it claims as the industry's fastest automated RTL power reduction technology |
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| RTL-to-GDSII reference flow optimised for 32/28nm
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2011-01-24 |
| Magma Design Automation says its hierarchical RTL-to-GDSII reference flow is now available for the Common Platform alliance's 32/28nm low-power process technology |
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| Sonic develops seamless SystemC-to-RTL design flow
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2006-06-14 |
| Sonics Inc.'s SonicsMX Smart Interconnect and SonicsStudio promise a seamless SystemC-to-RTL design flow |
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| RTL tech optimised for power-sensitive apps
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2011-11-15 |
| Apache unleashes the register-transfer-language (RTL) Power Model (RPM) claimed as a first-in-class technology geared to optimise power-sensitive applications |
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| C-to-RTL compiler to generate full-chip designs
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2007-01-10 |
| CebaTech Inc. plans to roll out the C2R Compiler, a C-to-RTL compiler that promises to generate full-chip designs |
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| Debug tool helps faster RTL closure
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2006-07-14 |
| Concept Engineering's RTLvision promises faster RTL code closure by delivering fast visualisation of critical design fragments and promoting easy understanding of design behaviour and design miss behaviour |
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| RTL power tool packs sequential analysis
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2009-09-02 |
| Calypto Design Systems Inc. has developed what it claims to be the most accurate register-transfer level (RTL) power analysis capability by applying its patented sequential analysis technology |
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| Tool automatically adds clock-gating logic to RTL code
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2007-03-28 |
| Claiming breakthrough technology in IC power optimisation, Calypto Design Systems is announcing PowerPro CG, a tool that automatically adds clock-gating logic to RTL code |
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| Verilog simulator offers faster RTL simulation
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2007-01-09 |
| Graphical debugging tool provider SynaptiCAD has released VeriLogger Extreme, a compiled-code Verilog 2001 simulator, priced at Rs.1.81 lakh ($4,000) on Windows platforms. |
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| Talus IC implementation system supports CPF
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2009-04-29 |
| Talus becomes the first RTL-to-GDSII flow to support both the CPF and the Unified Power Format |
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| Synopsys delivers 65nm ref flow for common platform initiative
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2006-07-21 |
| Synopsys Inc. has announced availability of its extended RTL-to-GDSII low-power reference design flow for the latest 65-nanometer (nm) process offered by the IBM |
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| New design flow for ARM Cortex-A8 processor from Synopsys
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2005-10-07 |
| Synopsys and ARM demonstrated the successful integration of Synopsys' Galaxy RTL synthesis, hierarchical design planning, physical implementation solution, sign-off and Discovery verification solution within a high-performance design flow for the new ARM Cortex-A8 processor |
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| Sequence enhances power analysis tool
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2008-10-24 |
| Sequence Design has added "timing-aware" RTL power analysis feature to its PowerTheatre power analysis and prototyping tool |
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| Sequence releases flagship product for better clock power
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2006-11-16 |
| Sequence Design has announced PowerTheater 65, its flagship product for RTL power estimation and management which includes enhanced clock power estimation and reduction, as well as improvements to stimulus generation and performance |
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| Tool enables full-chip assertion synthesis
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2010-05-11 |
| EDA start-up NextOp rolls out initial product, dubbed BugScope, a full-chip assertion synthesis product that automatically generate functional coverage properties from testbench and RTL |
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| Mentor touts first incremental FPGA synthesis tool
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2007-09-27 |
| Mentor Graphics has released the Precision RTL Plus Synthesis that enables designers to reach timing closure faster, minimise the impact of late cycle design changes and make efficient use of FPGA architectural blocks |
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| Atrenta deals with ESL synthesis
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2008-11-12 |
| Atrenta has announced the expansion of its "SpyGlass clean RTL" efforts to the ESL synthesis flow |
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| ON2 unveils multi-format hardware video decoder
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2008-02-14 |
| On2 Technologies has announced the release of the Hantro 8190 multi-format configurable hardware RTL video decoder for mobile phones |
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| Bluetooth IP offers three-fold transfer rates
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2007-07-05 |
| Wipro-NewLogic has introduced its Bluetooth 2.0+EDR base band RTL and software stack that offers three times higher transfer rates compared to Bluetooth 1.2 technology |
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| DSP design flow aims for medical imaging
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2011-09-16 |
| Altera presents model-based floating-point DSP design flow that integrates the algorithm modelling and simulation, RTL generation, synthesis, place and route, and design verification stages |
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| TBX eases co-verification for embedded systems
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2008-01-24 |
| Mentor has announced what it claims as the industry's only commercially proven RTL-accurate virtual emulation capability that eliminates the traditional barriers of adopting hardware in-circuit emulation for system-level integration |
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| Tools bridge chip design, verification with shared database
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2010-06-04 |
| Jasper's upgraded ActiveDesign and JasperGold tools bridge chip design and verification by sharing a common, persistent knowledge base. |
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| Cadence announces design flow for ARM Cortex-A8 processor
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2005-10-07 |
| Cadence Design Systems announced the immediate availability of a high-performance design flow for the new ARM Cortex-A8 processor. |
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| Design library target FPGA synthesis
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2008-05-29 |
| EVE introduced its DesignWare foundation library for use with FPGA synthesis software. |
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| Cray adopts Atrenta's SpyGlass for its ASIC projects
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2006-12-12 |
| Atrenta has recently announced that supercomputer provider Cray has adopted its SpyGlass platform for its next generation ASIC projects. |
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| Design system accelerates chip development
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2009-03-18 |
| Lynx is optimised for Synopsys' Galaxy Design Platform and is configurable to incorporate third-party technology. |
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| Actel optimises IP cores for radiation-tolerant FPGAs
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2006-05-23 |
| Actel Corp. has unveiled two IP cores optimised for use with the company's radiation-tolerant and firm-error immune FPGAs. |
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