| Aldec introduces multi-threaded VHDL compilation
|
2007-12-24 |
| Aldec has announced the release of Active-HDL 7.3 that includes multi-threaded HDL compilation, new waveform viewer and expanded VHDL 2006 construct support |
|
| IDE for VHDL boosts design productivity
|
2009-05-22 |
| Sigasi HDT contains an ultra-fast VHDL parser and compiler which run transparently in the background |
|
| Devt kit for customisable ARM9-based MCUs debuts
|
2007-09-20 |
| Atmel has introduced its FPGA devt kit that allows the simultaneous development and emulation of both the ARM9 software and FPGA Verilog/VHDL designs |
|
| IC emulator handles 10 crore gates at 20MHz
|
2007-01-24 |
| EVE SA has claimed to have developed the largest and fastest IC emulation product to date. ZeBu-XXL handles up to 100 million gates at up to 20MHz. |
|
| ESL tool tames one tough task: On-chip register design
|
2005-08-29 |
| Blueprint, an electronic system level tool from Denali Software, automatically generates and manages the vast number of on-chip control registers that users no doubt find themselves juggling. |
|
| Aldec rolls out ALINT 2008.10
|
2008-12-11 |
| Aldec Inc. says ALINT reduces risk when developing complex multi-million gate ASICs. |
|
| Yogitech announces OCP verification component
|
2006-10-04 |
| Yogitech SPA, a provider of design and verification technology, announced what it touts as the industry's first mixed-language Open Core Protocol UVC. |
|
| Reference design module improves jitter performance
|
2008-09-16 |
| National highlights a new video clock reference design, now available as a module for the Xilinx ML571. |
|
| MataiTech rolls out ESL tool to prevent bug at source
|
2006-08-18 |
| MataiTech LLC has rolled out Nauet, an ESL tool that lets hardware and software engineers collaborate at the earliest stages of a design, thus preventing bugs at the source. |
|
| Simulator supports Open IP Encryption
|
2006-07-14 |
| Aldec says its new version of the Riviera simulation tool supports design flows based on Synplicity's Open IP Encryption Initiative. |
|
| Verification sol'n eliminates JTAG pod connections
|
2011-05-30 |
| EVE integrates its hardware-assisted verification solution with the ARM VSTREAM Virtual Debug Interface eliminating the need for physical JTAG pod connections. |
|
| Synopsys testbench solution increases verification productivity
|
2005-09-30 |
| Synopsys announced Discovery Pioneer-NTB, a new SystemVerilog testbench automation tool that claims to increase verification productivity and improve the quality of complex SoC and IP designs. |
|
| Cadence unveils UCVs-line of reusable verification IP
|
2006-08-14 |
| Cadence Design Systems Inc. has introduced the UCVs, a new line of reusable VIP that integrates compliance management and mixed-language flexibility with advanced simulation-based testbench technology. |
|
| Getting the most from multiprocessor SoC design
|
2005-08-25 |
| Multiple processor designs are now found in a number of applications ranging from cellular phones and ink-jet printers all the way up to huge network routers. |
|
| Debugger improves FPGA power, speed and size tradeoffs
|
2005-10-12 |
| Impulse Accelerated Technologies has released its CoDeveloper Pro optimization and debugging software to complement its CoDeveloper C-to-FPGA compiler. |
|
| 1080p H.264 IP core eliminates external DRAM
|
2011-04-01 |
| Ocean Logic reveals the 1080p H.264 encoder and limited decoder IP core based on Compressed Frame Store (CFS) technology that eliminates external DRAM. |
|
| Xilinx announces DDR2 ref design
|
2006-02-07 |
| Xilinx Inc's DDR2-SDRAM interface uses the Virtex-4 ChipSync technology, a run-time calibration circuit that improves design margins and overall system reliability while reducing design cycles. |
|
| Simplorer 8.0 improves design performance
|
2009-05-27 |
| The Simplorer 8.0 features advanced modelling capabilities, including dynamic links to other Ansoft software. |
|
| Debug tool helps faster RTL closure
|
2006-07-14 |
| Concept Engineering's RTLvision promises faster RTL code closure by delivering fast visualisation of critical design fragments and promoting easy understanding of design behaviour and design miss behaviour. |
|
| Faster FPGAs roll for mobile devices
|
2010-02-22 |
| Programmable logic start-up SiliconBlue Technologies Corp. has launched a new series of FPGAs targeting mobile devices. |
|
| Dev't board prototypes designs in a snap
|
2009-09-23 |
| Altium rolls a new FPGA-based development board that eases instant prototyping of electronic designs. |
|
| Introduction to Programmable Systems on a Chip
|
2005-08-08 |
| There are a variety of programmable systems on a chip (SoCs) complete with underlying architectures and technologies. Tradeoffs exist between different programmable SoC devices |
|
| MataiTech's EDA tool offers OpenCores IP
|
2006-09-05 |
| Startup EDA vendor and design services provider MataiTech LLC has packaged OpenCores intellectual property (IP) with its fourth-generation EDA tool, Nauet 1.5. |
|
| Actel unveils block-based FPGA design
|
2007-06-20 |
| Actel Corp. is unveiling SmartDesign, a graphical design entry capability that lets users graphically create block diagrams from prefabricated blocks from Actel's DirectCore and SmartGen IP libraries, and supports custom blocks written in HDL code. |
|
| XMC module offers four SRIO ports
|
2008-11-27 |
| Innovative Integration has announced the X5-COM XMC IO module. |
|
| Actel unveils system mgmt tool for embedded apps
|
2007-08-13 |
| Actel's new reference design for embedded apps combines the instant-on mixed-signal Fusion PSC with the optimised, configurable soft CoreABC MCU core to provide a complete system mgmt solution. |
|
| 3U VPX FPGA boards accelerate algorithm processing
|
2011-05-24 |
| Acromag unveils VPX-VLX series of 3U VPX FPGA boards featuring a configurable Xilinx Virtex-5 FPGA enhanced with multiple high-speed memory buffers designed for accelerated algorithm processing. |
|
| Xilinx adds embedded, DSP, RT debug design flows to tool
|
2006-01-16 |
| Xilinx Inc. has announced that the availability of the ISE WebPACK 8.1i programmable logic design tool, which includes all the features of ISE Foundation with full support for embedded, DSP and real-time debug design flows. |
|
| Design library target FPGA synthesis
|
2008-05-29 |
| EVE introduced its DesignWare foundation library for use with FPGA synthesis software. |
|
| Multiprocessor design for SoCs
|
2005-09-23 |
| Allocating performance among all of the tasks in an SoC design provides greater design flexibility with multiple CPUs than with just one control processor and multiple blocks of logic. |
|
Strange modes of transport and other "stuff"
|
|
|IIC-China
|
|
|Electronic Components|Computer Products|Trade Show Center
|Site Feedback|Site Map|Help|About Us|Contact Us|Terms of Use|Privacy Policy|Security Commitment