Interfacing the Xicor X5163/323/643 CPU Supervisors to NEC 78K Microcontrollers
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2003-05-12 |
| This application note provides schematics and software used in interfacing Xicor's CPU supervisors to NEC's 78K series of microcontrollers |
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| Adding a manual reset to Xicor CPU supervisors
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2001-06-08 |
| This application note explores several different approaches in adding a manual reset to Xicor's CPU supervisors |
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| Applications of M16C/62 Flash CPU rewrite mode
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2003-09-19 |
| This application note describes using the CPU rewrite mode on the M16C/62 within a user program |
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| Designing with Xicor's X5000 series CPU supervisors
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2001-06-08 |
| This application note describes how to design a cost-effective CPU supervisor, which includes a watchdog timer, low voltage reset and power-on management, using Xicor's X5000 series |
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| Interfacing the Xicor X5163/323/643 CPU Supervisors to NEC 78K Microcontrollers
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2003-05-12 |
| This application note provides schematics and software used in interfacing Xicor's CPU supervisors to NEC's 78K series of microcontrollers |
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| Using the Xicor X5163/X5323/X5643 CPU supervisors with the 68HC11 microcontroller
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2003-05-12 |
| This application note demonstrates how the X5163/X5323/X5643 CPU supervisors can be interfaced to the 68HC11 microcontroller |
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| Using the Xicor X5163/X5323/X5643 CPU supervisors with the 68HC11 microcontroller
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2001-06-08 |
| This application note demonstrates how Xicor's CPU supervisors with EEPROM can be interfaced to the 68HC11 microcontroller |
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| Using the Xicor X5165/X5325/X5645 CPU supervisors with the 8051 microcontroller
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2001-06-08 |
| This application note describes how to interface the Xicor X5165/X5325/X5645 CPU supervisors to the 8051 microcontroller |
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| i.MX233 CPU and HCLK power saving features
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2010-03-02 |
| This application note describes the CPU Interrupt-Wait and the HCLK Auto-Slow features. It explains the procedure to enable each feature and also provides information about power saving |
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| Using the Xicor X5165/X5325/X5645 CPU supervisors with 8051 microcontroller
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2003-05-12 |
| 1 of 2www.xicor.comOctober, 2000 |
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| Determining CPU and memory requirements for real-time speech recognition systems using the TMS320C3x/C4x
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2001-05-08 |
| This application note describes the CPU and memory requirements for DSP real-time speech recognition systems using Texas Instruments' TMS320C3x and TMS320CC4x DSP families |
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| Interfacing the Xicor X5163/323/643 CPU supervisors to NEC 78K microcontrollers
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2001-06-12 |
| The Xicor CPU Supervisors have an on-chip program |
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| Adding a manual reset to Xicor CPU supervisors
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2001-06-08 |
| Adding a manual reset to Xicor CPU supervisors |
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| 3 Volt Intel StrataFlash Memory to NEC Vr4122 CPU Design Guide
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2003-06-28 |
| 3 Volt Intel StrataFlash Memory to NEC Vr4122 CPU Design Guide |
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| The Zilog datacom family with the 80186 CPU
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2000-11-27 |
| The Zilog datacom family with the 80186 CPU |
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| Designing with Xicor's X5000 series of CPU supervisors
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2003-05-12 |
| In recent years, product designs have changed rapidly. |
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| CPU supervisor and system management devices for battery applications: using the X40420, X40421 as a battery backup switch
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2009-09-18 |
| This application note explores the operation and use of the X40420's and X40421's function called battery switchover circuit. |
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| Reduce CPU overhead with intelligence interrupt arbitration (I2A) feature
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2004-11-25 |
| This app note describes the advantage of implementing the I2A and the operation of the arbitrating systems. |
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| Entering, leaving 24MHz operation for MCU
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2009-03-26 |
| Here's a set of best practices that should be used when changing the CPU speed to 24 MHz and responding to falling power supplies |
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| System reset (with built-in watchdog timers): Monolithic IC MM1099a
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2003-06-11 |
| This application note discusses the MM1096a IC, which is designed for variable CPU and MPU operations targeting low power supply applications |
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| Using SCC with Z8000 in SDLC protocol
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2000-11-27 |
| This application note describes the use of the Z8030 serial communications controller (SCC) with the Z8000 CPU to implement a communications controller in a synchronous data link control (SDLC) mode of operation |
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| System Reset - Monolithic IC PST598 series
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2003-06-18 |
| This application note discusses the PST596 to 598 monolithic ICs that accurately resets CPU systems after detecting the supply voltage at instantaneous power/surge conditions |
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| System Reset - Monolithic IC PST597 series
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2003-06-18 |
| This application note discusses the PST596 to 598 monolithic ICs that accurately resets CPU systems after detecting the supply voltage at instantaneous power/surge conditions |
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| System Reset - Monolithic IC PST596 - 598 series
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2003-06-18 |
| This application note discusses the PST596 to 598 monolithic ICs that accurately resets CPU systems after detecting the supply voltage at instantaneous power/surge conditions |
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| System Reset - Monolithic IC PST600 series
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2003-06-18 |
| This application note discusses the PST600 monolithic IC, which accurately resets CPU systems after detecting surge conditions |
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| "Shoot-through" in synchronous buck converters
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2010-02-19 |
| The synchronous buck circuit is in widespread use to provide point of use high current, low voltage power for CPU's, chipsets, peripherals etc |
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| Increasing system performance by leveraging the high end timer transfer unit
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2011-06-13 |
| Know how the High End Timer Transfer Unit can be used to offload tasks from the main CPU by doing transfers between the main memory and the NHET |
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| TMS320C6201/6701 DSP host port interface (HPI) performance
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2001-05-10 |
| This application note describes how to determine the number of CPU cycles required to transfer data between the host CPU and Texas Instruments' TMS320C6201/6701 DSPs using the Host Port Interface (HPI |
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| MPC553x, MPC555x and MPC556x family Nexus interface connector
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2010-03-25 |
| The IEEE-ISTO 5001-2003 Nexus standard (referred to as the Nexus standard) interface is an industry standard that crosses CPU boundaries and allows industry-standard tools to support multiple CPU architectures |
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| TMS320C671x/TMS320C621x EDMA performance data
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2004-06-16 |
| The enhanced DMA (EDMA) controller of the TMS320C621x/TMS320C671x devices is a highly efficient data transfer engine, capable of maintaining transfers at up to 1,800MBps at a 225MHz CPU clock frequency. This app note details actual bandwidth achieved under various operating conditions |
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Strange modes of transport and other "stuff"
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