Adding MCU into FPGA design
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2010-11-30 |
| Know how to instantiate an MCU directly into the HDL and used it immediately in a standard FPGA design flow without special scripts or complicated steps |
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| The role of distributed arithmetic in FPGA-based signal processing
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2001-04-12 |
| This application note derives the distributed arithmetic (DA) algorithm in embedding DSP functions in FPGA devices, and provides examples that illustrate its effectiveness in producing gate-efficient designs |
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| LM1771- and LM3880-based FPGA power supply solution
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2008-09-15 |
| This application note discusses the Virtex-5 FPGA power supply requirements |
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| ORCA Series 4 FPGA PLL Elements
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2002-11-20 |
| This application note discusses the ORCA Series 4 FPGA PLL Elements, designed for the delivery of networking IP |
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| ORCA series 3 to series 4 FPGA design conversion
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2002-12-06 |
| This application note outlines the caveats and steps for the successful migration of ORCA series 3 FPGA designs to ORCA series 4 |
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| Targeting Cypress PLDs from the Synopsys FPGA Express environment
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2001-03-29 |
| This application note demonstrates how to target Cypress Semiconductor's FLASH370i and Ultra37000 families of CPLDs using the synthesis and netlist capability of the Synopsys FPGA Express environment |
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| Programming an FPGA via e-mail
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2002-06-28 |
| This application note describes the process to program or reprogram an FPGA via an intranet or Internet connection |
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| Building Xtensa-based emulation system on Xilinx FPGA
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2008-09-29 |
| This application note describes how to map an Xtensa or Diamond core to an FPGA with a minimal on-chip system |
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| Interfacing the QDR to the Xilinx Spartan-II FPGA
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2001-03-27 |
| This application note introduces the enhanced Quad Data Rate (QDR) SRAM architecture, and describes the interface between this high-speed SRAM and the Xilinx Spartan-II FPGA |
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| Power complex FPGA-based systems with DC/DC µmodule regulator, Part 2
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2009-01-13 |
| Know how a modular approach that uses DC/DC conversion and current sharing delivers the output power while requiring minimal cooling. |
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| Implementing triple-rate SDI with Virtex-6 FPGA GTX transceivers
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2011-02-28 |
| Find out how to implement triple-rate SDI interfaces using Virtex-6 FPGAs. |
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| C code for interfacing AVR to AT17LVXXX FPGA configuration memories
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2004-12-02 |
| C code for interfacing AVR to AT17LVXXX FPGA configuration memories |
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| Interfacing FPGA to DAC with LVDS input
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2010-12-07 |
| Know how to interface a Fujitsu MB86064 DAC with parallel low-voltage differential signaling (LVDS) inputs to a Virtex-5 FPGA utilizing the dedicated I/O functions of the FPGA family |
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| Implement DDR2 SDRAM interface in FPGA
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2010-12-10 |
| Read about a 667 Mb/s DDR2 SDRAM interface implemented in a Virtex-5 device. |
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| Implementing triple-rate SDI with Spartan-6 FPGA GTP transceivers
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2011-02-21 |
| Learn how to implement triple-rate SDI interfaces using Spartan-6 FPGAs. |
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| DDR SDRAM controller using Virtex-4 FPGA devices
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2004-12-10 |
| This app note describes a 200MHz DDR SDRAM (JEDEC DDR400, PC3200 standard) controller implemented in a Virtex-4 XC4VLX25 FF668 -10 device. |
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| UTOPIA Level 3 in ORCA Series 3 FPGA
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2002-12-11 |
| This application note describes the functions and features of the Utopia Level 3 in ORCA Series 3 FPGAs |
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| SEU strategies for FPGA
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2010-12-08 |
| Know the strategies and representative calculations for handling single event upsets (SEUs), with an emphasis on reliability. |
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| Interface direct RF synthesis DAC to FPGA
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2009-01-06 |
| Know these techniques for interfacing the MAX5881, a 4.3Gsps cable downstream direct RF synthesis DAC, to FPGAs. |
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| Timing closure methodology for advanced FPGA designs
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2009-12-29 |
| This application note focuses on a generic methodology for timing closure. Whether you use ASSPs, ASICs or FPGAs, timing closure poses a challenge for system design. |
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| Implementing TMDS video interface in Spartan-6 FPGA
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2011-02-14 |
| Here's a set of reference designs able to transmit and receive DVI and HDMI data streams up to 1080 Mb/s using the native TMDS I/O interface featured by Spartan-6 FPGAs. |
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| FPGA interface to the TMSC6000 DSP platform using EMIF
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2004-12-10 |
| This app note presents the connection of Xilinx FPGAs to a Texas Instruments TMSC6000 DSP platform using the available external memory interface (EMIF). |
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| Implement UNH-IOL test suite compliance in FPGA GIGE
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2009-03-06 |
| Read about implementation details required for GIGE designs that do not use TSE MegaCore and require UNH-IOL compliance. |
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| Power FPGA-based systems with DC/DCµModule
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2009-05-14 |
| Read about LTM4601 DC/DCµModule regulators, which are self-contained and complete systems in an IC form factor. |
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| Power FPGA-based systems with DC/DCµModule, Part 2
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2009-05-14 |
| SHORT DESCRIPTION |
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| Power complex FPGA-based systems with DC/DC µmodule regulator
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2009-01-13 |
| Read about a modular approach that uses DC/DC conversion and current sharing to deliver the output power while requiring minimal cooling. |
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| Interfacing FPGA to JESD204A compliant ADC
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2010-12-06 |
| Know how to interface the Virtex-5 LXT, SXT, TXT, and FXT devices featuring GTP/GTX transceivers to an ADC compliant to JEDEC Standard |
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| Get smart about reset
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2008-11-20 |
| Here are the reasons why global reset for FPGA designs is not a good idea and should be avoided |
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| Drive ESCON with HOTLink
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2001-03-22 |
| This application note contains an overview of ESCON (Enterprise System CONnection) operation and a design example of ESCON physical interface implemented using HOTLink and a pASIC FPGA |
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| Power-up high-performance FPGAs
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2005-06-10 |
| This article explains FPGA power requirements and the causes of their power-up problems. Then it provides a strategy for powering FPGAs and offers guidance on selecting the appropriate point-of-load dc/dc converter for each power rail |
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Strange modes of transport and other "stuff"
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