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EE Times India - total search 15 articles sort by date sort by relevance

PCIE series Final Inch designs in PCI Express applications generation 1-2.5Gbps	2007-04-27
Loss is the main factor responsible for system degradation. The use of smaller trace widths, laminates with higher loss tangent, and sub optimal routing solutions with higher pair-to-pair coupling and additional via stubs reduces overall performance as well as the maximum allowable trace length. PCI Express systems uses a single Samtec PCIE Series through hole connector in a board-to-edge card configuration. When used with Samtec's Final Inch outing, breakout, and trace width solutions, the total trace lengths of PCIE series is within the limit of 13.9 inches
QPairs QTH-DP/QSH-DP Final Inch design in PCIe apps	2009-04-03
Here are measurement method applied to Final Inch designs and PCIe to help deploy systems of two PCB cards mated through electrical connectors
PCIE series Final Inch design in PCIe apps gen 2-5.0Gbps	2009-04-17
Here are measurement method applied to Final Inch designs and PCIe to help deploy systems of two PCB cards mated through electrical connectors
PCIE series Final Inch design in PCIe apps	2009-04-16
Here are measurement methods applied to Final Inch designs and PCIe to help deploy systems of two PCB cards mated through electrical connectors
PCIE series Final Inch designs in PCI Express applications Generation 2-5Gbps	2007-04-27
This document provides some tips to stress a typical interconnect design by stimulating their SPICE model components and devices with stressed data patterns. Stressing the system with reduced driver amplitude as well as jitter and noise injection ensures interoperability between PCI Express transmitter and receiver devices,
RiseUP RU8 Final Inch design in PCIe apps	2009-03-30
Here are measurement method applied to Final Inch designs and PCIe to help deploy systems of two PCB acrds mated through electrical connectors
SOPC builder PCIe design with GUI	2009-02-18
Know how to build an SOPC Builder system that includes a PCI Express MegaCore function and download it to a development board.
Final Inch designs in PCIe apps	2009-03-12
Here's a measurement method applied to Final Inch designs and PCIe to help engineers deploy systems of two PCB cards mated through electrical connectors
QPairs QTE-DP/QSE-DP Final Inch design in PCIe apps	2009-04-08
Here are measurement method applied to Final Inch designs and PCIe to help deploy systems of two PCB cards mated through electrical connectors
Edge Rate ERM8/ERF8 Final Inch design in PCIe apps	2009-04-09
Here are measurement method applied to Final Inch designs and PCIe to help deploy systems of two PCB cards mated through electrical connectors
Q2 QMS/QPS Final Inch design in PCIe apps	2009-04-08
Here are measurement method applied to Final Inch designs and PCIe to help deploy systems of two PCB cards mated through electrical connectors
Bus master DMA performance demo ref design for Xilinx PCIe	2011-02-18
Know how to design and implement a bus master direct memory access design using Xilinx PCI Express Endpoint solutions.
Bus Master DMA demo for PCIe	2010-11-23
Learn how to design and implement a Bus Master Direct Memory Access using PCI Express Endpoint solutions.
How to switch the DisplayPort hot-plug-detect signal with the MAX4928	2009-09-25
This application note explains that most DisplayPort switches have voltage level maxima that should not be exceeded and that a simple resistive divider cannot be used to meet logic levels for every application.
Tested computer list compatible w/ PXI, AXIe chassis	2012-01-06
Here's a personal computer and controller selection guide that enumerates the tested computers compatible with Agilent Technologies PXI and AXIe chassis.

---total search 15 articles, total 1 pages, The 1 Page---

EE Times Asia - total search 734 articles

Clock ICs geared for PCIe devices	2012-01-27
Micron buys storage virtualization startup	2012-01-26
Fanless computer optimized for 3G/WiFi/BT/GPS	2012-01-25
Impact of 4Gbps FireWire on industrial apps	2012-01-18
PCIe validation and compliance testing	2011-12-29
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