CDN220 high density I/O adapter user guide
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2001-10-05 |
| This application note discusses the features, functions, installation process and configuration of the CDN220 four-channel, DeviceNet-compatible I/O module |
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| Use LIN I/O slave with bit rate detection
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2009-04-17 |
| Here are about recommended setups for LIN slave applications as well as configuration hints and details of power consumption. |
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| Using dynamically programmable DRU for serial I/O
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2010-12-03 |
| Learn how to simulate and test a non-integer data recovery unit on a transceiver characterization platform. |
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| Eliminate I/O coupling effects when interfacing signals
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2008-11-26 |
| Know how to receive large-swing signals by design and address the parasitic leakage current behaviour. |
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| 3.3 V I/O issues in MCUs for automotive, industrial apps
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2011-12-06 |
| Read about some cost-effective interfacing techniques for inputs and outputs of 3.3 V microprocessors in an automotive environment. |
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| Digital I/O device for automated handler machine
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2009-01-27 |
| Know how to incorporate U2100A USB digital I/O device in an automated handler machine for a test system |
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| Remove I/O effects on FPGAs
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2010-11-24 |
| Read about different solutions to receive large-swing signals by design. |
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| Guide to using LatticeECP3 I/O interface
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2009-05-28 |
| Know how to use the capabilities of the LatticeECP3 devices to implement high-speed generic DDR interface, and the DDR, DDR2 and DDR3 memory interfaces. |
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| Video connectivity with TMDS I/O in FPGAs
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2008-11-24 |
| Here are reference designs for transmitting and receiving or HDMI data streams at 750Mbps. |
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| MC10X1189 I/O SPICE modeling kit
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2000-12-06 |
| This application note provides the SPICE information necessary to accurately model system interconnect situations for designs that utilize the MC10SX1189 Fibre Channel Coaxial Cable Driver and Loop Resiliency Circuit. |
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| MC10/100H600 translator family I/O SPICE modeling kit
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2000-12-06 |
| This application note provides the SPICE information necessary to accurately model system interconnect situations for designs, which utilize the translator circuits of the MC10H600 family. |
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| Implementation of a software UART on TMS320C54x using general-purpose I/O pins
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2001-05-16 |
| This application note discusses a software implementation of a UART to enable asynchronous communication with minimal hardware overhead using Texas Instruments' TMS320C54x DSP. |
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| Accessing status and control fields and I/O ports in the TMS320Cxx HLL debugger
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2001-05-04 |
| This application note discusses how the individual fields in the status registers of the TMS320Cxx HLL debugger can be observed in a convenient way. |
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| ASIC I/O test considerations
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2001-05-25 |
| This application note describes the difference between test and nontest I/Os. It also defines the requirements for boundary-scan cells associated with nontest I/Os. |
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| TMS320C6000 EDMA I/O scheduling and performance
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2004-06-16 |
| This app note details how to summarize, analyze and schedule system traffic to produce efficient enhanced DMA designs. |
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| I/O Using the TMS320C2xx asynchronous serial port in C
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2001-05-09 |
| This application note describes a program that demonstrates how to access the TMS320C2xx DSP asynchronous serial port from the Texas Instruments C compiler. |
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| Using an FX469 FFSK synchronous modem with an asynchronous data I/O
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2002-10-15 |
| This application note describes the construction of a low-cost asynchronous modem for the transmission of RS-232 data in the form of FFSK or MSK, between terminals by a radio or line medium. |
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| Set up I/O for test system
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2009-02-20 |
| Learn how to simplify test system integration by utilising open connectivity standards such as local area networking. |
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| FACT I/O model kit
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2000-12-05 |
| This application note provides the SPICE information necessary to allow the customer to perform system level interconnect modeling for the Motorola FACT logic family. It is not intended for the purpose of performing extensive device modeling. |
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| M16C/62: Automatic serial I/O transfer using DMA
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2001-10-09 |
| This application note briefly discusses the functions of the DMA controller for the M16C/62 MCU series. Operation of the UART and discussion on the firmware structure and its implementation to the MCU are explored. |
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| Use I/O port to implement IIC communication
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2009-06-04 |
| A method is introduced showing how a Holtek 8bit RISC MCU and related software can be used to implement a bus controller. |
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| Using a timer and I/O pins to interface 8051 MCUs with I²C serial EEPROMs
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2008-08-28 |
| This document provides source code to help the user implement the protocol with minimal effort. |
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| Using C and a timer to interface MSP430 MCUs with UNI/O bus-compatible serial EEPROMs
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2008-08-19 |
| As embedded systems become smaller, a growing need exists to minimise I/O pin usage |
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| Getting started converting .ABL files to VHDL
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2001-03-20 |
| This application note is intended to assist Warp users in converting designs written in DATA I/O's ABEL 7 HDL to IEEE 1076 VHDL |
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| H8/330 parallel-to-parallel print buffer controller
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2002-05-10 |
| This application note examines the usage of several on-chip peripherals, I/O ports and interrupt systems operating as a parallel-to-parallel print buffer controller |
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| Interface dsPIC33 DSCs with UNI/O serial EEPROMs
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2008-11-03 |
| UNI/O bus is a low-cost, easy-to-implement solution requiring only a single I/O pin for bidirectional communication |
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| Synthesisable CIO DDR RLDRAM II controller for Virtex-4 FPGAs
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2007-04-27 |
| Virtex-4 device is used to interface to Common I/O (CIO) Double Data Rate (DDR) Reduced Latency DRAM (RLDRAM II) devices. This application note describes reference design targetting two CIO DDR RLDRAM II devices at a clock rate of 200/235MHz with data transfers at 400/470Mbps per pin |
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| Using C and a timer to interface 8051 MCUs with UNI/O bus-compatible serial EEPROMs
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2008-08-21 |
| As embedded systems become smaller, a growing need exists to minimise I/O pin usage |
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| SONET rate conversion in Virtex-II Pro devices
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2002-06-28 |
| This application note targets Virtex-II Pro designs that require the direct use of Rocket I/O transceivers in 16-bit mode |
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| Interfacing baseline PIC MCUs with UNI/O bus-compatible serial EEPROMs
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2008-08-27 |
| As embedded systems become smaller, a growing need exists to minimise I/O pin usage |
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Strange modes of transport and other "stuff"
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