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EE Times India - total search 23 articles sort by date sort by relevance

Designing with the CY7C335 and Warp2 VHDL compiler	2001-03-19
This application note provides an overview of the CY7C335 Universal Synchronous EPLD architecture and Warp2 VHDL Compiler for PLDs
Abel-HDL vs. IEEE-1076 VHDL	2001-03-20
This application note compares and contrasts the complexity and basic features of Abel-HDL with those of IEEE-1076 VHDL
Getting started converting .ABL files to VHDL	2001-03-20
This application note is intended to assist Warp users in converting designs written in DATA I/O's ABEL 7 HDL to IEEE 1076 VHDL
Using hierarchy in VHDL design	2001-03-22
This application note describes VHDL's features, which are specifically designed to make hierarchical design both simple and powerful, and presents a simple example of how these features might be used
FIFO Dipstick using Warp2 VHDL and the CY7C371	2001-03-21
This application note presents a method by which FIFOs of any size may be monitored by an external PLD that will then generate all of the flags necessary for most FIFO applications.
ispLSI 8000V Family VHDL Code Examples	2002-10-11
This application note talks about the ispLSI8000V family architecture features and includes coding examples designed to allow the user to take advantage of its hardware capabilities.
FIFO Dipstick with Warp2 VHDL, CY7C371	2009-04-13
Here's a method by which FIFOs of any size may be monitored by an external PLD which will then generate all of the flags necessary for most FIFO applications.
The FLASH370i family of CPLDs and designing with Warp2	2001-03-19
This application note covers the following topics: a general discussion of complex programmable logic devices (CPLDs); an overview of the FLASH370i family of CPLDs; and using the Warp2 VHDL Compiler for the FLASH370i family
Implement two-dimensional rank order filter	2008-11-26
Here's a reference design that includes the RTL VHDL implementation of an efficient sorting algorithm
Building crosspoint switches with CoolRunner-II CPLDs	2002-06-28
This application note provides a functional description of the VHDL source code for a NxN digital crosspoint switch using a 128-macrocell CoolRunner-II CPLD
Method to instantiate and use a core in Warp with Cypress CPLDs	2001-03-20
This application note describes in detail how customers can incorporate cores in their system-level designs. It contains a detailed description of the steps required to instantiate VIF files in both VHDL and Verilog designs
An introduction to active-HDL Sim	2001-03-28
This application note provides a brief discussion to the Active-HDL Sim functional simulator. The discussion includes installing/uninstalling the simulator, creating an 1164/VHDL simulation model, the simulation process, and applying stimulus
Making designs 50% smaller	2008-11-12
Here's a design technique that can make a difference in the size and the performance of your FPGA design.
Using a UART to implement a 1-Wire Bus Master	2003-05-27
Using a UART to implement a 1-Wire Bus Master
Connecting Xilinx FPGAs to the Philips A-rate fiber-optic transceiver	2004-12-10
Connecting Xilinx FPGAs to the Philips A-rate fiber-optic transceiver
Interfacing the DS2760 1-Wire High Precision Li-Ion Battery monitor in a Microcontroller Environment	2002-12-06
Interfacing the DS2760 1-Wire High Precision Li-Ion Battery monitor in a Microcontroller Environment
Understanding chroma resampler	2010-12-02
Read about the implementation of six circuits necessary to perform commonly used conversions between various chroma formats.
Using the Ultra37000 ISR prototype board	2001-03-23
Using the Ultra37000 ISR prototype board
Connecting Xilinx FPGAs to the Philips A-rate fiber-optic transceiver	2004-12-10
Connecting Xilinx FPGAs to the Philips A-rate fiber-optic transceiver
CoolRunner-II for selecting video source	2008-11-10
Know how CoolRunner-II CPLD works as a logical switch that can select between different MPEG video sources.
DDR SDRAM DIMM interface for Virtex-II devices	2004-12-09
DDR SDRAM DIMM interface for Virtex-II devices
Connecting the Cypress VIC068/VAC068 to the TI TMS320C40: A prototype design	2001-03-30
Cypress Semiconductor Corporation 7 3901 North First Street 7 San Jose 7 CA 95134 7 408-943-2600
An Introduction to active-HDL FSM	2001-03-22
This application note provides an introduction to the Active-HDL FSM (finite state machine) editor, while highlighting key features of the software and illustrating the steps required to create a state machine.

---total search 23 articles, total 1 pages, The 1 Page---

EE Times Asia - total search 379 articles

How much decoupling should we use?	2012-05-02
Why compliance to PoE safety standards is crucial when moving beyond 60W	2012-01-31
Electronics trends in Asia: Opportunities and challenges	2012-01-19
How FPGAs boost medical imaging	2011-11-29
Altera initiates OpenCL program for FPGAs	2011-11-17
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