Multi-Vdd methodology reduces power at 65nm
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2008-10-23 |
| The power challenges at 65nm and smaller are significant. Here's what designers need to know about multi-Vdd to keep your design flow power-aware |
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| Ease production at 65nm with DFM
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2011-02-01 |
| Know the DFM tools and technologies that could ensure high yield manufacturing of analogue/ RF SoCs. |
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| Taking GALS to 65nm designs
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2004-11-16 |
| Emerging globally asynchronous, locally synchronous SoC design architectures offer a powerful way to solve interconnect issues in these superintegrated chips. |
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| Implement low-power 65nm FPGA designs
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2007-04-18 |
| This article explores the benefits of reduced power consumption. It also illustrates the many process and architectural innovations implemented in Virtex-5 devices. |
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| Analogue, mixed-signal connectivity IP at 65nm, below
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2007-05-07 |
| Here are some considerations in designing high-performance analogue/mixed-signal circuits with standard deep subµm CMOS technologies. |
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| Developing macrocell libraries in CMOS
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2005-09-16 |
| The Crolles2 Alliance brings resources together to develop macrocell libraries in 90nm and 65nm CMOS technologies |
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| Conquer loss, create high-yielding designs
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2007-03-23 |
| This article discusses the three most important yield-loss mechanisms in 65nm designs, and proposed methods for mitigating yield loss without severe impact on design schedules. Using tools that are both powerful and well-integrated, design and layout engineers can create high-yielding designs while meeting design specifications and demanding schedules |
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| Simulate RFIC designs with substrate parasitics
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2008-09-29 |
| Prepare and correlate substrate parasitics for 65nm low-power RF CMOS applications |
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| Updating DFT strategies for nanometre designs
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2007-06-16 |
| As the industry races toward 90nm and 65nm nodes, a "complete" solution with advanced test patterns and fault models is needed to improve defect detection |
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| Sub-100nm tech brings EDA opportunities
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2009-01-02 |
| Know the challenges in sub-100nm design and the tools that could improve designer's productivity. |
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| Video encoding for H.264 surveillance
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2009-03-05 |
| Know the architectural advantages of FPGAs for low-cost, yet high-performance video processing applications. |
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| Use Multi-Vt to cut leakage power in embedded SoC
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2011-08-16 |
| Here's a multi-threshold voltage flow technique that does not require embedded SoC architecture changes. |
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| Why use SONOS memory for eflash
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2011-10-13 |
| Read about the features of silicon-oxide-nitride-oxide-silicon memory technology that make it ideally suited for embedded Flash. |
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| Product tutorial: Reducing development time for infotainment apps
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2009-11-27 |
| A new range of devices from Renesas offers a multi-core and multi-IP design for increased scalability, a key consideration during software development. |
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| Looking at embedded trends: Non-volatile memory (Part 1)
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2010-01-06 |
| Here's a look at non-volatile memory, one of the three significant trends emerging in one of the most critical and competitive sockets in modern electronic systems. |
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| Target small delay defects with ATPG
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2010-03-03 |
| Test engineers are facing new test challenges at lower geometries and the small delay defects are one of them which pose a serious concern for maintaining good DPM levels. |
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| Lessons in time, cost savings from iPhone 3GS
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2009-06-29 |
| A more integrated—and probably lower cost—iPhone caused one analyst to quip the 'S' in 3GS may stand for savings. |
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| Billion-transistor full-custom designs
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2006-09-17 |
| Read about power integrity issues in today's advanced designs and the unique challenges of full-custom designs. |
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| Managing multi-Vt, multi-voltage domain timing/temp inversion
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2012-01-05 |
| As we move to 65 nm and below, it is important to choose the libraries corresponding to the lowest temperature PVT because of temperature inversion effects where the delay of the cell actually decreases with increase in temperature. |
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Strange modes of transport and other "stuff"
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