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EE Times India - total search 8 articles sort by date sort by relevance
Implement low-power 65nm FPGA designs 2007-04-18
This article explores the benefits of reduced power consumption. It also illustrates the many process and architectural innovations implemented in Virtex-5 devices.  
Taking GALS to 65nm designs 2004-11-16
Emerging globally asynchronous, locally synchronous SoC design architectures offer a powerful way to solve interconnect issues in these superintegrated chips.  
Analogue, mixed-signal connectivity IP at 65nm, below 2007-05-07
Here are some considerations in designing high-performance analogue/mixed-signal circuits with standard deep subµm CMOS technologies.  
Developing macrocell libraries in CMOS 2005-09-16
The Crolles2 Alliance brings resources together to develop macrocell libraries in 90nm and 65nm CMOS technologies  
Conquer loss, create high-yielding designs 2007-03-23
This article discusses the three most important yield-loss mechanisms in 65nm designs, and proposed methods for mitigating yield loss without severe impact on design schedules. Using tools that are both powerful and well-integrated, design and layout engineers can create high-yielding designs while meeting design specifications and demanding schedules  
Simulate RFIC designs with substrate parasitics 2008-09-29
Prepare and correlate substrate parasitics for 65nm low-power RF CMOS applications  
Updating DFT strategies for nanometre designs 2007-06-16
As the industry races toward 90nm and 65nm nodes, a "complete" solution with advanced test patterns and fault models is needed to improve defect detection  
Sub-100nm tech brings EDA opportunities 2009-01-02
Know the challenges in sub-100nm design and the tools that could improve designer's productivity.  

Embedded Design India - total search 3 articles
Product tutorial: Reducing development time for infotainment apps 2009-11-27
Lessons in time, cost savings from iPhone 3GS 2009-06-29
Video encoding for H.264 surveillance 2009-03-05
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Power Design India - total search 2 articles
Multi-Vdd methodology reduces power at 65nm 2008-10-23
Billion-transistor full-custom designs 2006-09-17
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EE Times Asia - total search 1187 articles
40nm 10GBASE-T PHYs operate at 4W/port 2010-02-08
IC biz slowdown drags fab tool market 2010-01-19
Analyst sees more acquisitions in IC world in 2010 2010-01-15
Targeting small delay defects 2010-01-13
SEMI: China could double IC production in 10 years 2010-01-11
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