Software debug options on ASIC cores
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1997-01-01 |
| Thinking about using ASIC technology to integrate your system's electronics onto a single chip? Not so fast. Now that electronics are reaching the level of integration that can be termed "systems on a chip," how will you debug your software |
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| The partitioning challenge of ASIC design into multiple FPGAs
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2010-02-12 |
| Partitioning a large ASIC design into multiple FPGAs can be challenging. Doing some upfront planning and selecting the right tool flow can make achieve a thoroughly verified ASIC and first-silicon success |
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| Using ISSP technology in structured ASIC design
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2003-12-16 |
| NEC's ISSP technology for designing structured ASIC has become popular with design engineers because of its easy-to-use design flow and clear road map for 90nm |
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| Achieve design flexibility using structured ASIC approaches
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2008-03-26 |
| This paper presents three options for various situations: Full Custom ASIC, FPGA, or Structured ASIC |
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| Optimizing ASIC design flow for SoPCs
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2001-05-01 |
| System-on-programmable-chip (SoPC) technology has characteristics of both board-based design and ASIC-based system-on-a-chip ASIC design. The immediate attraction of SoPC is that, like a breadboard, the design can be up and running very quickly |
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| Optimizing ASIC design flow for SoPCs
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2001-05-01 |
| System-on-programmable-chip technology has characteristics of both board-based design and ASIC-based SoC design. The immediate attraction of SoPC is that the design can be up and running very quickly |
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| The advantage of using logic BIST for ASIC designs
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2000-12-01 |
| This technical paper reveals the advantage of using logic BIST for ASIC designs |
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| Achieving cost savings in FPGA-to-ASIC conversion
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2006-09-06 |
| Planning an FPGA-to-ASIC conversion requires that the ASIC vendor is involved as early as possible in order to achieve the best cost savings |
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| Perform high-speed, low-cost prototyping of ASIC designs
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2009-10-30 |
| A "typical" ASIC design cycle is in the order of 9 to 18 months, while the window of opportunity for the introduction of a product using this device can be as little as two to four months |
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| Employing clock gating in ASIC, FPGA designs
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2010-06-16 |
| Clock gating is a well-understood power optimisation technique employed in both ASIC and FPGA designs to eliminate unnecessary switching activity |
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| ASIC generation revamped for IP reuse
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2001-06-01 |
| ASIC generation revamped for IP reuse |
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| Improve FPGA-based ASIC prototyping
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2009-01-13 |
| Know how to overcome the challenge of connecting all the logic blocks both within an FPGA and across multiple FPGA devices. |
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| FPGA-to-ASIC integration provides flexibility in auto MCUs
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2006-12-08 |
| The primary benefit of using MCUs has been high level system integration combined with relatively low cost. However, there are hidden costs associated with these devices well beyond the unit price. |
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| Hall-effect sensor/ASIC integration shrinks current transducers, Pt. 2
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2008-02-20 |
| Technology advances allow for flexibility in installation and use of these versatile current sensors. |
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| Employ dynamic power reduction in an ASIC
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2007-09-03 |
| Incorporate power-saving methods at multiple levels in application-specific IP. |
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| Hall-effect sensor/ASIC integration shrinks current transducers
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2008-02-20 |
| Technology advances allow for flexibility in installation and use of these versatile current sensors. |
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| Standard metal enables paradigm shift in ASIC technology
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2005-08-16 |
| Deep-submicron design and manufacturing issues drive the critical need for a new design technology to replace standard cell |
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| Single-chip analogue, digital TV ASIC verification
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2007-06-13 |
| Here are some questions and considerations on next-generation ATV and DTV ASICs. |
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| Using your wireless ASIC-AN18
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2004-05-13 |
| This app note shows that the P35-47-series of wireless ASICs are grouped into two families, the highly integrated transceiver ASICs and the amplifier/switch ASICs. |
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| Hall-effect sensor/ASIC integration shrinks current transducers (1
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2008-02-18 |
| Technology advances allow for flexibility in installation and use of these versatile current sensors. |
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| Top 10 methods for ASIC power minimization (2
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2007-01-10 |
| This is the second part of a two part article focusing on power minimization in deep submicron ASICs. It focuses on five effective implementation level low power techniques. |
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| Hall-effect sensor/ASIC integration shrinks current transducers
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2008-02-18 |
| Technology advances allow for flexibility in installation and use of these versatile current sensors. |
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| Top 10 methods for ASIC power minimization (1
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2007-01-08 |
| This is the first of a two-part article focusing on power minimization in deep submicron ASICs. It lists five of ten independent architectural power saving techniques and basic power consumption theories. |
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| Hardware implementations of multi-rate digital filters
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2001-04-01 |
| It is important to efficiently map interpolation and decimation functions into hardware. Here is a look at DSP, PLD, and ASIC implementations for multi-rate filters |
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| Choosing the right design flow model with integrated architecture
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2004-02-02 |
| Users of ASIC, COT and COPD models are finding that flows based on an integrated RTL-to-GDSII system can offer additional benefits when fully leveraged |
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| Verification IP reuse for complex networking ASICs
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2008-09-18 |
| Here is a verification environment that lays down the methodology blueprint for future ASIC verification projects and stretches the boundary of IP reuse |
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| Timing analysis tools greatly impacts a successful design
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2001-05-01 |
| Today, static timing analysis tools have matured to the point of handling significantly more complex design styles. This article examines the different kinds of timing analysis products used in ASIC, FPGA, and board-level design |
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| Timing closure: Hybrid optimization to the rescue
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2004-08-16 |
| Hybrid optimization combines ASIC cell-based design flow with transistor-level optimization to achieve improvement in timing closure |
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| HomePlug brings cost-effective power line networking
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2001-12-16 |
| This article describes how Ethernet-class networks over standard home power lines are advancing in the industry due entirely to the prevalent presence of ASIC-based signal processors |
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| Bluetooth Enabled ASICs Versus Standard Bluetooth Chipsets
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2001-07-02 |
| This paper discusses the pros and cons of using commercially available Bluetooth chipsets and integrating Bluetooth functionality into an existing ASIC |
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Strange modes of transport and other "stuff"
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