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EE Times India - total search 134 articles sort by date sort by relevance
Optimizing ASIC design flow for SoPCs 2001-05-01
System-on-programmable-chip technology has characteristics of both board-based design and ASIC-based SoC design. The immediate attraction of SoPC is that the design can be up and running very quickly  
The advantage of using logic BIST for ASIC designs 2000-12-01
This technical paper reveals the advantage of using logic BIST for ASIC designs  
Software debug options on ASIC cores 1997-01-01
Thinking about using ASIC technology to integrate your system's electronics onto a single chip? Not so fast. Now that electronics are reaching the level of integration that can be termed "systems on a chip," how will you debug your software  
ASIC generation revamped for IP reuse 2001-06-01
ASIC generation revamped for IP reuse  
Hall-effect sensor/ASIC integration shrinks current transducers 2008-02-20
Technology advances allow for flexibility in installation and use of these versatile current sensors.  
Single-chip analogue, digital TV ASIC verification 2007-06-13
Here are some questions and considerations on next-generation ATV and DTV ASICs.  
Standard metal enables paradigm shift in ASIC technology 2005-08-16
Deep-submicron design and manufacturing issues drive the critical need for a new design technology to replace standard cell  
Using your wireless ASIC-AN18 2004-05-13
This app note shows that the P35-47-series of wireless ASICs are grouped into two families, the highly integrated transceiver ASICs and the amplifier/switch ASICs.  
Top 10 methods for ASIC power minimization (2 2007-01-10
This is the second part of a two part article focusing on power minimization in deep submicron ASICs. It focuses on five effective implementation level low power techniques.  
Hall-effect sensor/ASIC integration shrinks current transducers (1 2008-02-18
Technology advances allow for flexibility in installation and use of these versatile current sensors.  
Top 10 methods for ASIC power minimization (1 2007-01-08
This is the first of a two-part article focusing on power minimization in deep submicron ASICs. It lists five of ten independent architectural power saving techniques and basic power consumption theories.  
Verification IP reuse for complex networking ASICs 2008-09-18
Here is a verification environment that lays down the methodology blueprint for future ASIC verification projects and stretches the boundary of IP reuse  
Hardware implementations of multi-rate digital filters 2001-04-01
It is important to efficiently map interpolation and decimation functions into hardware. Here is a look at DSP, PLD, and ASIC implementations for multi-rate filters  
Analyzing dynamic voltage drop at 90 nm and beyond 2007-08-06
As VLSI technology scales to 90 nanometres and beyond, ASIC vendors increasingly see power grid integrity issues in their designs and in the field, for two primary reasons  
Choosing the right design flow model with integrated architecture 2004-02-02
Users of ASIC, COT and COPD models are finding that flows based on an integrated RTL-to-GDSII system can offer additional benefits when fully leveraged  


 
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