A practical approach to reusing HDL code in FPGA designs
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2005-12-28 |
| Smart FPGA designers have realised that it is more practical to recycle existing HDL code. This paper discusses how to reuse existing code that was not initially designed for reuse |
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| Extend peripheral set of embedded processors
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2004-12-01 |
| System designers define and integrate peripheral subsystems without writing HDL using the SOPC Builder tool |
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| Speed up down-converter implementation with rapid prototyping
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2008-07-17 |
| Using the right EDA tools, performance can be simulated, analysed and design characteristics automatically converted to generic HDL code appropriate for synthesis and FPGA implementation |
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| Use processor-driven tests for functional verification
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2006-10-04 |
| This article discusses processor driven test bench methods in detail and presents their strengths and weaknesses. It examines the inherent value of combining PDT with traditional HDL test benches |
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| Unifying hardware, software verification
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2009-03-05 |
| Explore the need for a unified platform for both hardware and embedded software development. |
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| Syntax raises RTL abstraction level
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2001-05-16 |
| A University of Toronto professor has proposed a new RTL abstraction syntax that he claimed can be implemented by a modest extension to traditional imperative programming languages. |
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| Optimizing ASIC design flow for SoPCs
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2001-05-01 |
| System-on-programmable-chip technology has characteristics of both board-based design and ASIC-based SoC design. The immediate attraction of SoPC is that the design can be up and running very quickly. |
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| Developing a design methodology for embedded memories
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2001-01-01 |
| Developing a design methodology for |
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| Back to the language roots
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2005-01-02 |
| It's not time for the revolution yet. Traditional hardware-description languages have specific features that make them superior to software programming languages; although SystemC has its place in the hardware-design process, it still can't compete with Verilog and VHDL. |
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| Designing improved DC/DC regulator using FPGA
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2011-11-18 |
| The availability of affordable low-powered FPGAs coupled with analogue-to-digital converters allows the FPGA to replace the traditional analogue approach. |
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| Fundamentals of core-based FPGA design (Part 1)
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2011-08-22 |
| The first instalment of this series provides an overview of FPGA processor core types—firm, hard and soft—and the pros and cons that need to be evaluated in the context of an embedded system's requirements. |
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| How to rapidly debug serial buses in FPGAs
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2009-07-15 |
| Read about common debugging issues and learn how to resolve them. |
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| Analog, mixed-signal design flow found wanting
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2001-06-16 |
| Different views cloud the current analog/mixed-signal design flow issue and should stop concentrating on the problem but find a lasting solution for the industry to further prosper. |
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| Speed up processor verification with testbench infrastructure reuse
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2011-09-01 |
| Specialised processor verification IP can free engineers from historical development and maintenance commitments. This liberated time and energy can then allow a renewed focus on verification quality and turnaround times. |
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| Speed enhancements for Model Tech upgrades
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2001-04-15 |
| This article discusses the ModelSim simulation upgrade, which promises faster performance, better memory use, new interactive debug features and improved testbench and regression test support. |
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| Power-Sensitive Design Techniques On FPGA Devices
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2001-07-03 |
| Power-Sensitive Design Techniques On FPGA Devices |
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| Optimizing ASIC design flow for SoPCs
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2001-05-01 |
| System-on-programmable-chip (SoPC) technology has characteristics of both board-based design and ASIC-based system-on-a-chip ASIC design. The immediate attraction of SoPC is that, like a breadboard, the design can be up and running very quickly. |
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| Verification firm starts partners program
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2001-04-15 |
| Seeking deeper integrations with third-party EDA tools, Verisity Design Inc. announced its Verisity Interoperability Partners (VIP) program. This technical article discusses that program and its effect to the EDA industry. |
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| Technical intro to functional qualification, Part 2
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2009-04-08 |
| Read about functional qualification and how it is related to mutation analysis. |
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| Employ FPGA to accelerate medical imaging process
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2011-09-01 |
| Know how to use an FPGA platform and a high level synthesis tool called Impulse C to accelerate a statistical line of reaction estimation for a high-resolution PET scanner. |
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| Verification tech captures automotive expertise
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2005-09-01 |
| The automotive industry calls for modern verification techniques as the proliferation of electronic gadgetry adds to rising IC complexity in cars |
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| Design RFICs faster, accurately
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2006-11-16 |
| A middle-of-the-road approach to RFIC design balances top-down fast design processes with bottom-up silicon accuracy to produce a predictable schedule and first-pass silicon. |
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| Equivalence checking for SoC blocks
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2001-11-16 |
| This technical article explains that as custom blocks become increasingly important for SoCs, equivalence checking between transistor-level implementation and behavioral modeling become equally significant design factors. |
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| Developing a video emulation environment
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2002-01-01 |
| This technical article describes the relevance of employing verification and emulation to video communications design and the IC capable of providing standards-based motion video encoding and decoding for real-time video conferencing apps. |
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| ALF language lets designers control libraries
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2004-05-17 |
| Without ALF, EDA tools could not overcome the deficiencies by proprietary, tool-specific and fragmentary library extensions. |
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| Formal verification for IP soft core
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2003-11-17 |
| Engineers are facing challenges on improving design efficiency and shortening time-to-market of IP soft core--formal verification is believed to provide a new solution for them. |
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| One approach for debugging of modified designs
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2001-03-01 |
| Two engineers describe a methodology of comparing old designs to new designs in order to validate the new one. |
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| Solving problems early on using co-verification
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2004-11-16 |
| Learn the importance and benefits of hardware and software co-verification before the physical design becomes available. |
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| Vector generation for structural testers
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2004-12-01 |
| Sizing of modern ASICs and SoCs requires an array of vectors for comprehensive testing to achieve the required quality levels. |
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| Transaction-based simulation using SystemC/SCV
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2005-03-16 |
| Learn how SystemC/SCV speeds up simulation and verification cycles to provide overall project cycle with better quality results |
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Strange modes of transport and other "stuff"
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