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EE Times India - total search 22 articles sort by date sort by relevance
A practical approach to reusing HDL code in FPGA designs 2005-12-28
Smart FPGA designers have realised that it is more practical to recycle existing HDL code. This paper discusses how to reuse existing code that was not initially designed for reuse  
Speed up down-converter implementation with rapid prototyping 2008-07-17
Using the right EDA tools, performance can be simulated, analysed and design characteristics automatically converted to generic HDL code appropriate for synthesis and FPGA implementation  
Use processor-driven tests for functional verification 2006-10-04
This article discusses processor driven test bench methods in detail and presents their strengths and weaknesses. It examines the inherent value of combining PDT with traditional HDL test benches  
Optimizing ASIC design flow for SoPCs 2001-05-01
System-on-programmable-chip technology has characteristics of both board-based design and ASIC-based SoC design. The immediate attraction of SoPC is that the design can be up and running very quickly.  
Syntax raises RTL abstraction level 2001-05-16
A University of Toronto professor has proposed a new RTL abstraction syntax that he claimed can be implemented by a modest extension to traditional imperative programming languages.  
Developing a design methodology for embedded memories 2001-01-01
Developing a design methodology for  
Verification firm starts partners program 2001-04-15
Seeking deeper integrations with third-party EDA tools, Verisity Design Inc. announced its Verisity Interoperability Partners (VIP) program. This technical article discusses that program and its effect to the EDA industry.  
Technical intro to functional qualification, Part 2 2009-04-08
Read about functional qualification and how it is related to mutation analysis.  
Speed enhancements for Model Tech upgrades 2001-04-15
This article discusses the ModelSim simulation upgrade, which promises faster performance, better memory use, new interactive debug features and improved testbench and regression test support.  
Analog, mixed-signal design flow found wanting 2001-06-16
Different views cloud the current analog/mixed-signal design flow issue and should stop concentrating on the problem but find a lasting solution for the industry to further prosper.  
Developing a video emulation environment 2002-01-01
This technical article describes the relevance of employing verification and emulation to video communications design and the IC capable of providing standards-based motion video encoding and decoding for real-time video conferencing apps.  
Solving problems early on using co-verification 2004-11-16
Learn the importance and benefits of hardware and software co-verification before the physical design becomes available.  
Verification tech captures automotive expertise 2005-09-01
The automotive industry calls for modern verification techniques as the proliferation of electronic gadgetry adds to rising IC complexity in cars  
Transaction-based simulation using SystemC/SCV 2005-03-16
Learn how SystemC/SCV speeds up simulation and verification cycles to provide overall project cycle with better quality results  
Design RFICs faster, accurately 2006-11-16
A middle-of-the-road approach to RFIC design balances top-down fast design processes with bottom-up silicon accuracy to produce a predictable schedule and first-pass silicon.  

Embedded Design India - total search 11 articles
Simulation debugging using triple speed Ethernet testbench 2009-12-18
Unifying hardware, software verification 2009-03-05
Embedding 1-Wire Master into ASIC 2008-12-22
Using the embedded JTAG ACE player 2008-11-10
Back to the language roots 2005-01-02
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Power Design India - total search 1 articles
Power-Sensitive Design Techniques On FPGA Devices 2001-07-03
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EE Times Asia - total search 286 articles
64bit simulator handles larger designs 2010-01-22
FPGA-based dev't board eases prototyping 2009-09-23
Altera, Peking U open joint EDA/SOPC Lab 2009-08-17
Tool suite speeds up multiprocessor apps design 2009-06-22
65nm FPGAs, clock ICs defy downturn 2009-02-26
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