Optimise I/O expansion in workstations
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2007-12-16 |
| PCIe switches and PCI-to-PCIe bridges can help get beyond many of the workstation I/O limitations. Let's look at how these devices can be used to optimise I/O expansion in high-performance workstations |
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| Grasp the ins and outs of high-speed I/O
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2004-06-01 |
| While serial I/O would seem to solve the interconnect dilemma facing high-speed designs, parallel interfaces still have their place |
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| FPGA Mezzanine card enables I/O design flexibility
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2009-11-17 |
| Today's embedded system designers continue to rely on FPGAs to perform the increasingly critical role of external I/O interface for their systems |
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| Choosing digital I/O for your output sensor
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2004-05-17 |
| Classify digital output sensors based and point out the critical parameters that should be taken into account when selecting a digital I/O module for your application |
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| I/O gating versus sleep modes
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2006-09-20 |
| Here are the differences between CPLDs with an I/O gating feature, and the "sleep modes" used by FPGAs |
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| Creating a third generation I/O interconnect
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2004-09-01 |
| This paper looks at the success of the widely adopted PCI bus, and describes a higher performance next-generation I/O interconnect |
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| Overcome FPGA I/O pin assignment challenges
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2009-03-13 |
| Remove the pain from the pinout process with a mix of smart I/O planning and new tools |
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| Unleashing the power of flexible I/O pin mapping
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2007-11-16 |
| Through software, an MCU's features can come to the forefront with minimal design tradeoffs. This article discusses the use of software to map and re-map I/O pins |
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| Embedded test offers unique value for serial I/O
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2007-08-02 |
| Although incorporating high-speed serial buses into embedded systems solves many problems, the design and validation processes differ and aren't well understood. |
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| Testing dimensional limits of high I/O flip-chip design
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2001-02-01 |
| The study characterizes underfill materials, examining some large package geometries and design manufacturing processes to avoid defects for I/O counts |
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| Enhancing computer-based I/O for test systems
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2001-09-16 |
| This technical article describes a change in the test and measurement arena as computer-based I/O systems makes their debut |
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| QoS for video delivery in shared-I/O
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2009-03-12 |
| Here's a look at QoS's role in consolidated/converged systems and the challenges in implementing it. |
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| Embedded test aids serial I/O design
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2007-08-16 |
| Although incorporating high-speed serial buses into embedded systems solves many problems, the design and validation processes differ and aren't well understood. Here's an article that explains them. |
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| Reduce cost, get I/O connectivity in comms system
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2008-11-21 |
| Know the advantages of using PCIe end-point and PCIe-native silicon solutions. |
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| The power of flexible I/O pin mapping unleashed
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2007-11-02 |
| Through software, an MCU's features can come to the forefront with minimal design tradeoffs. |
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| Optimizing I/O protection for ADSL modems
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2003-05-16 |
| By utilizing ordinary phone lines, ADSL tools need protection from electrical risks such as lightning stresses and other power hazards. |
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| Innovative Digital I/O Signal Switching Technology
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2001-07-02 |
| This paper describes the JAZiO digital signal switching technique for low-latency, high-bandwidth applications, such as DRAMs, SRAMs, CPUs, ASICs, SoCs, etc. |
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| Twiddle bits
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2001-12-03 |
| It's amazing what you can do with a single general-purpose I/O pin. Join us for a comprehensive look at the possibilities |
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| Virtualise with InfiniBand
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2008-08-14 |
| This article explains how I/O virtualisation using InfiniBand and Channel I/O Virtualisation (CIOV) complements current and future virtualisation ecosystem developments with standard implementations |
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| Abstracting device-driver development
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2004-05-03 |
| An abstraction layer makes a convenient interface between device drivers and I/O hardware |
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| I/Os for distributed automation control
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2005-03-16 |
| This article describes the idea of the industrial CAN I/O module and the data exchange between connected modules being done using a CAN bus |
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| Enhance MCU performance with DMA-based system controller
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2010-03-10 |
| To be able to handle the high data rates and frequencies of real-time I/O and peripherals, MCUs must achieve higher processing efficiency |
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| Using FPGAs for high-speed serial interface design
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2003-03-17 |
| FPGA provides the bandwidth and flexibility for industry leading high-speed interfaces. Its True-LVDS technology was designed to support the strict timing requirement of up to four high-speed differential I/O protocols |
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| How to simplify industrial process control systems (Part 1)
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2009-08-28 |
| This article examines the key performance requirements of process-control systems and the analogue I/O modules they contain—and introduces an industrial process-control evaluation system that integrates these building blocks using the latest IC technology |
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| Modelling for accurate Serdes design
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2007-12-16 |
| This paper describes an algorithmic modelling methodology that gives you flexibility in modelling your serial I/O device accurately while providing you with all the IP protection you need |
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| How to simplify industrial process control systems (Part 2)
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2009-09-10 |
| Here's part two of an article that examines the key performance requirements of process-control systems and the analogue I/O modules they contain |
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| Cadence, Agere tool would foster IC co-design
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2001-05-01 |
| This article describes the Cadence and Agere team-up to develop a tool with chip I/O planning capabilities |
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| Wireless chip-to-chip link shows promise
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2004-11-16 |
| Proximity Communication is an implementation of such a scalable I/O technology that uses the lithographic pitch of on-chip wires |
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| Infiniband requires design trade-offs
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2000-12-01 |
| As the Internet explosion continued unabated over the last five years, the IT industry has struggled to keep up with the relentless demand for higher bandwidth, availability and decreased cost. PCI has been the workhorse of the computer I/O systems that link server Mips to terabytes of storage and GBps of Internet transmission bandwidth |
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| Achieve 533MHz FPGA memory data rates
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2009-09-09 |
| This article examines the architecture behind the I/O blocks in high-end FPGAs and how these FPGAs are able to achieve 533MHz or 1,067Mbit/s data rates |
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Strange modes of transport and other "stuff"
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