Verification IP reuse for complex networking ASICs
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2008-09-18 |
| Here is a verification environment that lays down the methodology blueprint for future ASIC verification projects and stretches the boundary of IP reuse |
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| Vendors must support IP reuse in SoC
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2003-04-16 |
| The need for IP reuse will increase as design complexity grows to higher levels. This support structure forms an invisible layer that would make SoC/IP-ASIC engagements as seamless as possible |
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| ASIC generation revamped for IP reuse
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2001-06-01 |
| ASIC generation revamped for IP reuse |
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| Deal with complexity of hardware design project management
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2011-10-05 |
| Read about an approach to combat the problems of IP management, remote site performance, inconsistent deployment, IP reuse and designer collaboration |
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| QIP metric streamlines reuse
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2006-02-16 |
| The process of evaluating and integrating IP to maximize benefits of reuse is as important as the decision to reuse |
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| Fitting last year's IP to today's processes
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2001-06-01 |
| Changing design styles in IP reuse should prompt engineers to be more receptive to future design shifts in the industry |
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| Speed handset test with adaptive test case
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2008-11-21 |
| Adaptive test case methodology allows reuse of test IP across test cases, handset platforms and operating systems |
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| Designing digital video broadcast and wireless systems with common FPGA building blocks
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2008-02-13 |
| Common IP building blocks for FPGAs make it easier for designers to implement one system for DTV and reuse and modify the same building blocks for other data communication applications |
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| Analog, mixed-signal design flow found wanting
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2001-06-16 |
| Different views cloud the current analog/mixed-signal design flow issue and should stop concentrating on the problem but find a lasting solution for the industry to further prosper. |
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| Adaptive reuse: Plan, adopt, apply
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2009-03-17 |
| The desirability of reuse can significantly change depending on the time horizons that an ROI analysis chooses |
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| Using LTE on FPGAs
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2009-02-19 |
| Read about LTE's features and know how FPGA may address the increased processing demands of this specification. |
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| Logic suppliers seek ways to embed FPGAs
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2001-03-01 |
| Driven by the convergence of communications, computing and consumer applications, SoC design complexity increases the time required to bring competitive products to market, putting a premium on design speed and flexibility. |
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| Ensuring the accuracy of third-party IP
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2006-10-01 |
| The best and most unambiguous measure of functional correctness is the extent to which IP has been validated in silicon production. The article discusses the most basic need of every chip designer—functionally correct IP |
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| Silicon prototyping verifies IP functions
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2001-06-01 |
| SoC designers are confronting several important tasks in optimizing next-generation products. New systematic approaches are needed to ensure that IP can be transferred from one process geometry to the next |
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| Fundamentals of core-based FPGA design (Part 1)
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2011-08-22 |
| The first instalment of this series provides an overview of FPGA processor core types—firm, hard and soft—and the pros and cons that need to be evaluated in the context of an embedded system's requirements. |
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| Researchers team up for Java-based IP query tool
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2001-05-16 |
| A collaborative effort is producing a new Java-based tool that promises to allow users to easily query IP repositories and commercial databases via the Web |
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| Trim down turnaround time with hierarchical timing analysis
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2011-10-19 |
| Read about a technology that enables hierarchical STA by performing accurate block-level timing analysis in the top-level context. |
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| SoCs likely to pose heading-off test problems
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2000-12-01 |
| This technology news article describes the problems and solutions test engineers should face when confronting SoC designs. |
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| IP devt, FPGA prototyping with SystemC/TLM
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2009-03-18 |
| Here's a design flow that starts with highly abstracted models to cycle RTL models of IP |
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| Single-mask simplicity needed for SoC
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2001-06-01 |
| The move to multimillion-gate chips made it necessary to adopt design-reuse strategies for new SoC devices |
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| T/TCP is protocol of choice for transaction apps
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2003-09-16 |
| T/TCP is protocol of choice for transaction apps |
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| Overcome design complexities in multi-core networking (Part 2)
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2009-10-01 |
| This article discusses in more detail how multi-core can be used for a new design for 4G telecommunications infrastructure and for a network offload engine for an existing SIP server. |
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| Packet rings aim at metro nets
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2001-05-01 |
| Resilient packet ring (RPR) is a new technology that optimizes unique requirements of metro networks by defining a MAC with two network interfaces. |
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| Windows NT And Windows 2000 For Real-Time Applications
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2001-07-03 |
| For many reasons, Windows NT, NT Embedded and Windows |
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| SuperHyway provides SoC backbone
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2000-12-01 |
| A step ahead of CompactPCI, Compact Packet Switching Backplane (cPSB) is emerging as a viable solution for interconnect problems. |
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| Real system-level design challenge: Hardware-firmware integration
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2001-06-16 |
| For today's engineering co-design, the real system challenge is the hardware/firmware integration. |
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| Shift from FPGAs for prototype to ASICs for production
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2011-12-16 |
| The idea of migrating an FPGA design into an ASIC can be overwhelming to a design team, but careful planning can significantly ease the process. |
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| Employ FPGA to accelerate medical imaging process
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2011-09-01 |
| Know how to use an FPGA platform and a high level synthesis tool called Impulse C to accelerate a statistical line of reaction estimation for a high-resolution PET scanner. |
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| SuperHyway provides SoC backbone
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2000-12-01 |
| Recent technology improvements have made it cost-effective to integrate components previously connected on a PCB onto a single piece of silicon. These so-called system-on-a-chip (SoC) devices generally comprise most of the blocks commonly found on a computer motherboard plus some application-specific intellectual property (IP). This means design issues that were formerly the province of systems designers are now within the realm of the chip architect. As a result, interconnection schemes common at the system and network level, such as packet switching, must now be considered at the SoC level |
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| Achieve cache coherence in MIPS32 multi-core design
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2008-12-01 |
| Read about design methods for facilitating design reuse centred on an open standard |
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Strange modes of transport and other "stuff"
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