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EE Times India - total search 41 articles sort by date sort by relevance
Vendors must support IP reuse in SoC 2003-04-16
The need for IP reuse will increase as design complexity grows to higher levels. This support structure forms an invisible layer that would make SoC/IP-ASIC engagements as seamless as possible  
Verification IP reuse for complex networking ASICs 2008-09-18
Here is a verification environment that lays down the methodology blueprint for future ASIC verification projects and stretches the boundary of IP reuse  
ASIC generation revamped for IP reuse 2001-06-01
ASIC generation revamped for IP reuse  
QIP metric streamlines reuse 2006-02-16
The process of evaluating and integrating IP to maximize benefits of reuse is as important as the decision to reuse  
Deal with complexity of hardware design project management 2011-10-05
Read about an approach to combat the problems of IP management, remote site performance, inconsistent deployment, IP reuse and designer collaboration  
Fitting last year's IP to today's processes 2001-06-01
Changing design styles in IP reuse should prompt engineers to be more receptive to future design shifts in the industry  
Designing digital video broadcast and wireless systems with common FPGA building blocks 2008-02-13
Common IP building blocks for FPGAs make it easier for designers to implement one system for DTV and reuse and modify the same building blocks for other data communication applications  
Speed handset test with adaptive test case 2008-11-21
Adaptive test case methodology allows reuse of test IP across test cases, handset platforms and operating systems  
Analog, mixed-signal design flow found wanting 2001-06-16
Different views cloud the current analog/mixed-signal design flow issue and should stop concentrating on the problem but find a lasting solution for the industry to further prosper.  
Adaptive reuse: Plan, adopt, apply 2009-03-17
The desirability of reuse can significantly change depending on the time horizons that an ROI analysis chooses  
Ensuring the accuracy of third-party IP 2006-10-01
The best and most unambiguous measure of functional correctness is the extent to which IP has been validated in silicon production. The article discusses the most basic need of every chip designer—functionally correct IP  
Logic suppliers seek ways to embed FPGAs 2001-03-01
Driven by the convergence of communications, computing and consumer applications, SoC design complexity increases the time required to bring competitive products to market, putting a premium on design speed and flexibility.  
Silicon prototyping verifies IP functions 2001-06-01
SoC designers are confronting several important tasks in optimizing next-generation products. New systematic approaches are needed to ensure that IP can be transferred from one process geometry to the next  
Using LTE on FPGAs 2009-02-19
Read about LTE's features and know how FPGA may address the increased processing demands of this specification.  
Achieve cache coherence in MIPS32 multi-core design 2008-12-01
Read about design methods for facilitating design reuse centred on an open standard  
Overcome design complexities in multi-core networking (Part 2) 2009-10-01
This article discusses in more detail how multi-core can be used for a new design for 4G telecommunications infrastructure and for a network offload engine for an existing SIP server.  
Researchers team up for Java-based IP query tool 2001-05-16
A collaborative effort is producing a new Java-based tool that promises to allow users to easily query IP repositories and commercial databases via the Web  
Fundamentals of core-based FPGA design (Part 1) 2011-08-22
The first instalment of this series provides an overview of FPGA processor core types—firm, hard and soft—and the pros and cons that need to be evaluated in the context of an embedded system's requirements.  
SuperHyway provides SoC backbone 2000-12-01
Recent technology improvements have made it cost-effective to integrate components previously connected on a PCB onto a single piece of silicon. These so-called system-on-a-chip (SoC) devices generally comprise most of the blocks commonly found on a computer motherboard plus some application-specific intellectual property (IP). This means design issues that were formerly the province of systems designers are now within the realm of the chip architect. As a result, interconnection schemes common at the system and network level, such as packet switching, must now be considered at the SoC level  
Windows NT And Windows 2000 For Real-Time Applications 2001-07-03
For many reasons, Windows NT, NT Embedded and Windows  
SuperHyway provides SoC backbone 2000-12-01
A step ahead of CompactPCI, Compact Packet Switching Backplane (cPSB) is emerging as a viable solution for interconnect problems.  
Employ FPGA to accelerate medical imaging process 2011-09-01
Know how to use an FPGA platform and a high level synthesis tool called Impulse C to accelerate a statistical line of reaction estimation for a high-resolution PET scanner.  
Trim down turnaround time with hierarchical timing analysis 2011-10-19
Read about a technology that enables hierarchical STA by performing accurate block-level timing analysis in the top-level context.  
Packet rings aim at metro nets 2001-05-01
Resilient packet ring (RPR) is a new technology that optimizes unique requirements of metro networks by defining a MAC with two network interfaces.  
Single-mask simplicity needed for SoC 2001-06-01
The move to multimillion-gate chips made it necessary to adopt design-reuse strategies for new SoC devices  
Speed up processor verification with testbench infrastructure reuse 2011-09-01
Specialised processor verification IP can free engineers from historical development and maintenance commitments. This liberated time and energy can then allow a renewed focus on verification quality and turnaround times  
T/TCP is protocol of choice for transaction apps 2003-09-16
T/TCP is protocol of choice for transaction apps  
OCP's role in multi-core designs 2008-11-19
Learn about the Open Core Protocol that is expected to address today's multi-core problems.  
Of ARM Mali-T604 and the future IP trends 2011-07-12
The ARM Mali graphics core has made a shift from years of evolution in the rendering hardware. It now points to the future of IP  
SoCs likely to pose heading-off test problems 2000-12-01
This technology news article describes the problems and solutions test engineers should face when confronting SoC designs.  


Max's Cool Beans

Clive Maxfield Strange modes of transport and other "stuff"

Someone just pointed me at a YouTube video that claims to show the world's first e-powered multicopter flight...

 

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