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EE Times India - total search 26 articles sort by date sort by relevance
Verification IP reuse for complex networking ASICs 2008-09-18
Here is a verification environment that lays down the methodology blueprint for future ASIC verification projects and stretches the boundary of IP reuse  
Vendors must support IP reuse in SoC 2003-04-16
The need for IP reuse will increase as design complexity grows to higher levels. This support structure forms an invisible layer that would make SoC/IP-ASIC engagements as seamless as possible  
ASIC generation revamped for IP reuse 2001-06-01
ASIC generation revamped for IP reuse  
QIP metric streamlines reuse 2006-02-16
The process of evaluating and integrating IP to maximize benefits of reuse is as important as the decision to reuse  
Fitting last year's IP to today's processes 2001-06-01
Changing design styles in IP reuse should prompt engineers to be more receptive to future design shifts in the industry  
Designing digital video broadcast and wireless systems with common FPGA building blocks 2008-02-13
Common IP building blocks for FPGAs make it easier for designers to implement one system for DTV and reuse and modify the same building blocks for other data communication applications  
Speed handset test with adaptive test case 2008-11-21
Adaptive test case methodology allows reuse of test IP across test cases, handset platforms and operating systems  
Analog, mixed-signal design flow found wanting 2001-06-16
Different views cloud the current analog/mixed-signal design flow issue and should stop concentrating on the problem but find a lasting solution for the industry to further prosper.  
Logic suppliers seek ways to embed FPGAs 2001-03-01
Driven by the convergence of communications, computing and consumer applications, SoC design complexity increases the time required to bring competitive products to market, putting a premium on design speed and flexibility.  
Ensuring the accuracy of third-party IP 2006-10-01
The best and most unambiguous measure of functional correctness is the extent to which IP has been validated in silicon production. The article discusses the most basic need of every chip designer—functionally correct IP  
Silicon prototyping verifies IP functions 2001-06-01
SoC designers are confronting several important tasks in optimizing next-generation products. New systematic approaches are needed to ensure that IP can be transferred from one process geometry to the next  
Packet rings aim at metro nets 2001-05-01
Resilient packet ring (RPR) is a new technology that optimizes unique requirements of metro networks by defining a MAC with two network interfaces.  
Windows NT And Windows 2000 For Real-Time Applications 2001-07-03
For many reasons, Windows NT, NT Embedded and Windows  
SuperHyway provides SoC backbone 2000-12-01
A step ahead of CompactPCI, Compact Packet Switching Backplane (cPSB) is emerging as a viable solution for interconnect problems.  
T/TCP is protocol of choice for transaction apps 2003-09-16
T/TCP is protocol of choice for transaction apps  

Embedded Design India - total search 5 articles
Adaptive reuse: Plan, adopt, apply 2009-03-17
Achieve cache coherence in MIPS32 multi-core design 2008-12-01
OCP's role in multi-core designs 2008-11-19
Real system-level design challenge: Hardware-firmware integration 2001-06-16
SuperHyway provides SoC backbone 2000-12-01
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Power Design India - total search 1 articles
SuperHyway provides SoC backbone 2000-12-01
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EE Times Asia - total search 212 articles
Industry focuses on core competencies, cutting costs 2010-01-12
MicroSD card brings extreme gaming into handsets 2009-11-17
Xilinx adopts ARM processors, interconnect tech 2009-10-22
Korea firm turns to Tower for foundry services 2009-10-15
Braving software-to-silicon verification challenges at 45nm 2009-10-05
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