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EE Times India - total search 13 articles sort by date sort by relevance
Scaling JTAG to evolving embedded needs 2006-08-09
JTAG adoption and integration requires a strategy across multiple development disciplines to ensure a standard approach that you can re-use and build on in later generations of the product. This article describes how JTAG is used in various generations of system development and design  
Testing SoC interconnects using boundary scan 2004-08-02
Delay violations occurring in the interconnects of high-speed SoCs can be tested using JTAG boundary scan architecture  
Logic suppliers seek ways to embed FPGAs 2001-03-01
Driven by the convergence of communications, computing and consumer applications, SoC design complexity increases the time required to bring competitive products to market, putting a premium on design speed and flexibility.  
PI-IPM cuts motor drive design time, risk 2003-08-18
power  
Uncovering hidden chip costs 2007-10-22
For some consumer electronics manufacturers, ICs are the single largest contributor to finished-goods costs. An understanding of the chip supplier's cost structures can bolster the OEM's negotiating position.  
Startup preps 5Gbps backplane transceiver 2001-06-16
In a bid to build a better bit pipe on the backplane, Accelerant Networks is preparing to roll out a proprietary CMOS transceiver that harnesses multilevel signaling technology.  
Breeding smart multimedia for a mobile world 2004-09-16
Breeding smart multimedia for a mobile world  
Simplifying LVDS Backplane Design In 3G Wireless Basestations 2001-04-03
The increasing demand for bandwidth is driving the communi-  
Monitor-based debugging 2002-03-02
A ROM monitor is an inexpensive, but powerful, debugging aid. Follow these steps to make a basic monitor even more powerful.  
Integrating personal technologies in automobiles 2004-10-18
Integrating personal technologies in automobiles  
The advantage of using logic BIST for ASIC designs 2000-12-01
This technical paper reveals the advantage of using logic BIST for ASIC designs.  
FPGA on-chip debug with off-chip benefits 2003-02-17
This article will address some of the limitations of on-chip debug and show users an alternative that combines the best of both worlds--on-chip debug with off-chip, deep sample storage.  
COT design flow validates SoCs 2002-05-01
This technical article details the approach two chip companies used to validate a COT (customer-owned tool) flow from beginning to end resulting in a complete working silicon.  

Embedded Design India - total search 34 articles
Simplified programming of Altera FPGAs using a SCANSTA111/112 JTAG scan chain mux 2009-12-30
Using multiple boundary scan port linker (BSCAN2) 2009-10-28
MSC81xx and MSC711x JTAG connectivity 2009-09-02
Automatically initializing data segment values in MAX-IDE 2009-08-19
LatticeXP2 security usage guide 2009-07-02
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Power Design India - total search 8 articles
Debugging MSP430 LPM4.5 2010-02-01
Powering up and programming the ProcessorPM ispPAC-POWR605 2010-01-22
ispPAC-POWR1208P1 evaluation board PAC-POWR1208P1-EV 2009-09-22
Configure the ispPAC-POWR1220AT8 device 2009-07-02
In-circuit programming of EEPROM-based system monitors 2009-01-29
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EE Times Asia - total search 333 articles
Dev't tool offers easy-to-use interface for ARM MCUs 2010-01-29
Anti-tamper protection for Cyclone III LS devices 2010-01-06
WLAN ref design enables straightforward board boot 2010-01-05
Prototype peripheral board eases FPGA design 2009-12-08
MCUs deliver easy-to-use USB connectivity 2009-12-03
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