Lithography

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EE Times India - total search 24 articles sort by date sort by relevance

Scatterometry-based critical dimension and profile metrology	2002-09-16
This technical article discuss how as geometries are pushed below 0.15m, critical dimensions and feature profile metrology has become key to overall control of lithography
Panasonic Blu-Ray DVD players move to 45nm	2007-11-13
Choosing a DVD player is not as easy a decision as choosing a television. This is because of the additional investments needed to enjoy the player, such as movies to watch, increases the cost.
NAND flash preps for 4 bits per cell	2007-10-29
Adoption of MLC technology for NAND flash has been a crucial factor in achieving bit growth of NAND flash devices.
Recognising density requirements at 28 nm	2012-04-02
Density has transitioned from a back-end manufacturing concern that was of little interest to designers to an issue that affects the layout of standard cell libraries.
Full-spectrum brightfield inspection uncovers IC defects	2007-09-16
This article demonstrates that a tunable broadband brightfield approach has several advantages over a single-wavelength approach for meeting new inspection challenges and generating higher capture rates of yield-impacting defects.
No innovation wall for 25nm MLC NAND	2010-04-05
While most pundits have speculated that NAND has hit the wall, IM Flash Technologies continued their aggressive path scaling with the 25nm 8Gbyte, 2bit/cell MLC NAND.
Library generators employ optical correction at cell level	2001-03-01
This technology article discusses the enhancement of cell-based designs with the evolution of EDA.
Moving active components inside the board	2006-07-03
Shrinking PCB real estate has spurred research into embedding electronic components within the board. Tom Adams describes the work of a consortium led by the Fraunhofer Institute.
Single-mask simplicity needed for SoC	2001-06-01
The move to multimillion-gate chips made it necessary to adopt design-reuse strategies for new SoC devices.
NAND flash preps for 4 bits per cell	2007-10-29
Adoption of MLC technology for NAND flash has been a crucial factor in achieving bit growth of NAND flash devices.
Evolution of manufacturing closure for advanced nodes (Part 1)	2011-02-07
Here's an article series on the various challenges of manufacturing closure at advanced nodes.
Intel StrataFlash wireless memory (L30) to Intel PXA26x processor family design guide	2004-05-14
Intel StrataFlash wireless memory (L30) to Intel PXA26x processor family design guide
Design-manufacturing synergy will win yields in the nm era	2008-03-01
IC Design has grown increasingly complex with the advent of the nanometre era. Yield success is much harder to achieve because of the increased number and complexity of variables affecting manufacturability.
Inside the Sony Rolly's groove	2008-08-05
Gregory Quirk examines the "dancing" MP3 player to see how it gets its groove.
Achieve accurate modelling using IBIS	2007-02-01
This paper provides a discussion on how to create accurate IBIS models.
Optimizing DSPs for wireless world	2001-04-15
Complexities in next-generation requirements is taxing the capabilities of traditional DSP technology and design methodologies, causing a need for industry business models to be drastically redefined.
Sub-100nm tech brings EDA opportunities	2009-01-02
Know the challenges in sub-100nm design and the tools that could improve designer's productivity.
What the next transistor will be like	2011-08-01
Here's a comprehensive discussion on the race is on to redefine the transistor.
Use thicker copper to achieve high-current drive in power ICs	2011-05-09
Find out how thicker copper needed for higher currents and voltages can be implemented in power IC design.
Stir manufacturing into design effectively	2007-03-28
Semiconductor companies looking to maximise yield will need to deploy more effective methods to account for manufacturing effects early in IC development.
Beyond pass/fail: Exploring device failures	2005-03-16
DFT will soon be used for reliable device-failure analysis and become the keystone of rapid yield improvement
Overcome sub-90nm challenges	2005-12-05
New tools in comprehensive design flows are needed for reliable silicon performance of sub-nanometer designs.
Tackling physical verification below 90nm	2005-05-02
The article reviews the key challenges of physical verification below 90nm and the methodologies needed to tackle them
Solder paste process control for CSPs and 0201s	2003-01-16
This technical article discusses a more effective strategy to improve first pass yields and prevent defects from occurring in CSPs and 0201s.

---total search 24 articles, total 1 pages, The 1 Page---

EE Times Asia - total search 779 articles

Ultra-thin films open new possibilities in flexible electronics	2012-05-17
TSMC shifts from multiple to single-only process at 20nm	2012-04-20
Addressing integration concerns with SiP technologies	2012-04-17
Maximizing 10GBase-T connectivity in data centers (Part 2)	2012-04-13
Suss MicroTec buys projection litho tool vendor	2012-04-09
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